Results 11 to 20 of about 1,665 (175)
Improved bilayer phosphorene TFET inverter performance by reduction of ambipolarity
AIP Advances, 2018 A comprehensive study on the degradation of inverter output voltage based on double-gated (DG) bilayer Phosphorene complementary tunnel-FETs is presented.
Dip Joti Paul, Quazi D. M. Khosru
doaj +2 more sources
Core-Shell TFET Developments and TFET Limitations
2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2019 Tunneling field-effect transistors (TFET) based on a vertical gate-all-around (VGAA) nanowire (NW) architecture with a core-shell (CS) structure have been explored for future CMOS applications. Performance predictions based on a tight-binding mode-space NEGF technique include a drive current $\mathrm{I}_{\mathrm{o}\mathrm{n}}$ of $6.7\ \mu \mathrm{A}
M. Passlack +8 more
openaire +2 more sources
Simulation Based Investigation of Triple Heterojunction TFET (THJ-TFET) for Low Power Applications
Silicon, 2022 We designed a new model tunnel feld-efect transistor (TFET) based on Triple Heterojunction Tunnel Field Efect Transistor (THJ-TFET) is investigated and designed in this paper.
Armstrong Joseph J. +6 more
openaire +2 more sources
Drive Current Enhancement in TFET by Dual Source Region [PDF]
Journal of Electrical and Computer Engineering, 2015 This paper presents tunneling field-effect transistor (TFET) with dual source regions. It explores the physics of drive current enhancement. The novel approach of dual source provides an effective technique for enhancing the drive current.
Zhi Jiang +4 more
doaj +2 more sources
Applied Sciences, 2020 In this paper, analysis and optimization of surrounding channel nanowire (SCNW) tunnel field-effect transistor (TFET) has been discussed with the help of technology computer-aided design (TCAD) simulation.
Seung-Hyun Lee +5 more
doaj +2 more sources
The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
Nanoscale Research Letters, 2017 The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM).
Wei Li +4 more
doaj +2 more sources
3T-TFET bitcell based TFET-CMOS Hybrid SRAM design for Ultra-Low Power Applications
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016 This paper presents a TFET/CMOS hybrid SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like IoT (Internet of Things). A novel 3-Transistor TFET SRAM cell is used for array while CMOS for periphery. The simulation extractions for power and speed are done including wiring and device parasitic capacitance ...
Gupta, Navneet +4 more
openaire +4 more sources
Performance Evaluation of Epitaxial Layer Based Gate Modulated TFET (GM-TFET) [PDF]
Silicon, 2021 Abstract This paper reports the performance of an epitaxial layer (ETL) based gate modulated (GM-TFET) through 3D Technology Computer Aided Design (TCAD) simulations. The architecture utilizes effects of both vertical tunneling and lateral tunneling phenomena to improve the device performance.
Rajesh Saha +3 more
openaire +1 more source
Temperature characteristics of Gate all around nanowire channel Si-TFET [PDF]
, 2021 This paper study the impact of working temperature on the electrical characteristics of gate all around nanowire channel Si-TFET and examines the effect of working temperature on threshold voltage, transcondactance (gm), ION/IOFF ratio, drain induced ...
Hashim, Yasir +2 more
core +1 more source
Temperature characteristics of Gate all around nanowirechannel Si-TFET
, 2023 This paper study the impact of working temperature on the electrical characteristicsof gate all around nanowire channel Si-TFET and examines the effect of working temperatureon threshold voltage, transcondactance (gm), ION/IOFF ratio, drain induced ...
Firas Natheer (16958826)
core +1 more source