Results 51 to 60 of about 1,965 (222)
A New On-Chip ESD Strategy Using TFETs-TCAD Based Device and Network Simulations
IEEE Journal of the Electron Devices Society, 2018 For the first time, this paper reports the quasi-static behavior and the applicability of the tunnel field effect transistor (TFET) for the on-chip electrostatic discharge (ESD) protection. ESD evaluations are performed on 28-nm fully depleted silicon-on-
Radhakrishnan Sithanandam +1 more
doaj +1 more source
Design of 7T SRAM Using InGaAs-Dual Pocket-Dual Gate-Tunnel FET for IoT Applications
IEEE Access, 2023 The Internet of Things (IoT) is becoming increasingly popular in areas like wearable communication devices, biomedical devices, and home automation systems.
Gadarapulla Rasheed +1 more
doaj +1 more source
Atomic Layer Deposition in Transistors and Monolithic 3D Integration
Advanced Functional Materials, Volume 36, Issue 41, 21 May 2026.Transistors are fundamental building blocks of modern electronics. This review summarizes recent progress in atomic layer deposition (ALD) for the synthesis of two‐dimensional (2D) metal oxides and transition‐metal dichalcogenides (TMDCs), with particular emphasis on their enabling role in monolithic three‐dimensional (M3D) integration for next ...
Yue Liu +5 more
wiley +1 more source
Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications [PDF]
, 2016 International audienceIn this paper, we propose a novel TFET Flip-Flop (TFET-FF) designed to address the requirements of ULP (Ultra-Low-Power) applications, like IoT (Internet of Things), while maintaining high performance.
Makosiej, Adam +9 more
core +1 more source
Emerging single‐element ferroelectrics: From theory to experiment
InfoMat, Volume 8, Issue 4, April 2026.This review explores recent developments in single‐element ferroelectrics, covering mechanisms of ferroelectric behavior, their crystal structures, key preparation methods, ferroelectric performance characteristics, and promising device applications in field‐effect transistors, photodetectors, and visual perceptrons.
Run Zhao +7 more
wiley +1 more source
IEEE Journal of the Electron Devices Society, 2019 Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction tunneling field-effect transistor (TFET).
Aryan Afzalian +4 more
doaj +1 more source
Investigation of gate leakage current in TFET: A semi-numerical approach
Alexandria Engineering Journal, 2023 Tunneling FET (TFET) has been demonstrated as a favorable candidate to replace conventional MOSFETs in low-power applications. However, there are many challenges that should be overcome to efficiently operate the TFET.
N.M.S. Tawfik +6 more
doaj +1 more source
Advanced Electronic Materials, Volume 12, Issue 5, 9 March 2026.Sub‐5 nm double‐gate MOSFETs based on 2D SiAs monolayers are investigated using quantum transport simulations. By engineering source‐drain underlap regions, the devices achieve exceptional on‐currents of up to 1206 µA µm−1, surpassing the ITRS 2028 high‐performance targets.
Dogukan Hazar Ozbey, Engin Durgun
wiley +1 more source
Impact of process and device dimensions on Bio-TFET Sensitivity [PDF]
, 2019 This paper reports the impact of process and dimensions on the sensitivity of the double gate Bio-TFET for drain and source underlap structures. The Bio-TFET is simulated using different dielectric permittivity materials localized over the drain to gate ...
Agopian, P. G.D. [UNESP] +2 more
core +1 more source
From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits [PDF]
, 2021 International audienceIn this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology.
Taco, Ramiro +4 more
core +1 more source