Results 61 to 70 of about 1,665 (175)
Undoped vertical dual-bilayer TFET with a super-steep sub-threshold swing: proposal and performance comparative analysis [PDF]
In this paper, the undoped vertical dual-bilayer tunnel field effect transistor (UV-DBL-TFET) at a low operating voltage (0.5 V) is introduced, and its DC and RF performance parameters are compared with those of the conventional charge plasma-based ...
Sunny Anand +9 more
core +1 more source
Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET
We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation.
Abdullah Al Mamun Mazumder +3 more
doaj +1 more source
This study presents a numerical quantum transport analysis of graphene nanoribbon field‐effect transistors (GNRFETs) using the non‐equilibrium Green's function (NEGF) formalism. The results show that reducing the channel length and optimizing dielectric materials, such as HfSiO4, significantly enhance ON‐state current and the Ion/Ioff ratio.
Mahamudul Hassan Fuad
wiley +1 more source
High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor
A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel ...
Xiaoling Duan +6 more
doaj +1 more source
HfO2‐based ferroelectric materials are promising for next‐generation memory technologies by providing outstanding performance aligning with data‐centric computing needs. This review details recent advancements in materials, devices, and integration for HfO2‐based memories, with the goal of identifying both the technological opportunities and remaining ...
Zuopu Zhou +9 more
wiley +1 more source
CMOS Sensor Nodes with Sub-PicoWatt TFET Memory
International audienceThis paper describes the applicability of Tunnel FETs (TFET) to ultra-low-power sensor-node embedded Static Random-Access Memories (SRAM).
Makosiej, Adam +4 more
core +1 more source
Temperature Impact on The ION/IOFF Ratio of Gate All Around Nanowire TFET [PDF]
This research paper presents the effect of working temperature on the ION, IOFF and ION/IOFF ratio of gate all around nanowire TFET. The (Silvaco) simulation tool has been used to investigate the temperature characteristics of a transistor.
Hashim, Yasir +5 more
core +1 more source
Configurable Electrostatically Doped High Performance Bilayer Graphene Tunnel FET
A bilayer graphene-based electrostatically doped tunnel field-effect transistor (BED-TFET) is proposed. Unlike graphene nanoribbon TFETs in which the edge states deteriorate the OFF-state performance, BED-TFETs operate based on bandgaps induced by ...
Fan W. Chen +4 more
doaj +1 more source
A high‐density and highly‐reliable capacitive time‐domain (TD) content‐addressable memory (CAM) based on a single ambipolar ferroelectric memcapacitor with band‐reject‐filter‐shaped capacitance‐voltage characteristics is proposed. The proposed TD CAM performs linear Hamming distance computation via propagation delay modulation, achieving improved ...
Minjeong Ryu +5 more
wiley +1 more source
Analytical Approach and Simulation of GaN Single Gate TFET and Gate All around TFET
In this work, we investigate the impact of Gallium Nitride (GaN) based Single Gate Tunnel field effect transistors (SG TFET) and Gate All Around (GAA) TFET by using analytical models. The models are derived by solving the 2D-Poisson’s equation and Parabolic Approximation Technique.
T.S.Arun Samuel +2 more
openaire +2 more sources

