Results 101 to 110 of about 117,069,527 (207)
A Configurable Resolution Time-to-Digital Converter with Low PVT Sensitivity for LiDAR Applications
This paper presents an all-digital and configurable resolution time-to-digital converter (TDC) with low process–voltage–temperature (PVT) sensitivity for light detection and ranging (LiDAR) applications.
Cheng-I Cheng +4 more
core +1 more source
A Multihit Time-to-Digital Converter Architecture on FPGA
, 2009 We present a multihit time-to-digital converter (TDC) architecture implemented in a field-programmable gate array (FPGA) with minimized timing overhead. The TDC circuit provides two-level fine-time interpolation.
Khouas, Abdelhakim +2 more
core
Applied SciencesLong-range single-photon LiDAR requires both a wide time-of-flight (ToF) dynamic range and fine temporal resolution, while the nonuniform fine-time bins of FPGA carry-chain tapped delay lines (TDLs) can introduce systematic errors into time ...
Tong Xue +6 more
doaj +1 more source
A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL
IEEE AccessThe phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen +4 more
doaj +1 more source
, 2021 The revival of the experiments at the LHC collider at CERN will call on increasingly efficient detectors in order to face the challenge of increase in the number of collisions. This increase will lead to more confusion of products from different collisions.
openaire +1 more source
A magnetic field to digital converter using PWM and TDC techniques
, 2013 [[abstract]]A high resolution magnetic-?eld-to-digital converter (MDC) is presented. It is composed of a magnetic-?eld-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector.
Chien-Hung Kuo;Shr-Lung Chen;Shen-Iuan Liu
core
In recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate~(MAC) is considered a {\textit de facto} unit operation in NNs. By leveraging the inherent parallel processing capabilities of CiM, NNs that require numerous MAC operations can be executed more ...
Challagundla, Dhandeep +2 more
openaire +2 more sources
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
, 2013 The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X-axis phases and Y-axis phases (based on 2-D definition) can be used, rather than only ...
Liscidini, Antonio +8 more
core +1 more source
A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
, 2011 Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation.
Liscidini, Antonio +3 more
core +1 more source
High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA
IEEE AccessIn recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs).
Lorenzo Castelvero +2 more
doaj +1 more source