Results 111 to 120 of about 1,742 (210)

An all-digital PLL with a first order noise shaping Time-to-Digital Converter

, 2020
-This paper presents an All Digital PLL (ADPLL) based on a first order noise shaping Time-to-Digital Converter (TDC). The architectures of two state-of-art ADPLLs and a stateof-art Gated Ring Oscillator (GRO) TDC are described.
Francesco Brandonisio, Franco Maloberti
core  

A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

, 2015
2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ...
Liu, Yao-Hong, Staszewski, Robert Bogdan, Wang, Bindi, et al., Harpe, Pieter   +4 more
core   +1 more source

Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS

, 2011
WiMAX (Worldwide Interoperability for Microwave Access) is the emerging wireless technology standard of the near future, which enables high speed packet data access.
Effendrik, P. (author)
core  

A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL

IEEE Access
The phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen, Hao Zheng, Daniel O'Hare, Deepu John, Barry Cardiff   +4 more
doaj   +1 more source

A magnetic field to digital converter using PWM and TDC techniques

, 2013
[[abstract]]A high resolution magnetic-?eld-to-digital converter (MDC) is presented. It is composed of a magnetic-?eld-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector.
Chien-Hung Kuo;Shr-Lung Chen;Shen-Iuan Liu
core  

High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA

IEEE Access
In recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs).
Lorenzo Castelvero, Ignacio H. Lopez Grande, Valerio Pruneri   +2 more
doaj   +1 more source

Controle digital de um condicionador de tensão alternada usando PLL para obtenção do sinal de referência [PDF]

, 2007
Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-graduação em Engenharia Elétrica.O objetivo maior desse trabalho é realizar um estudo e projeto de um condicionador indireto de tensão alternada ...
Gomes, Carlos Eduardo Marcussi
core  

Power-efficient time-to-digital converter for all-digital frequency locked loops

, 2015
An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This ...
Vesterbacka, Mark,, Andersson, Niklas,
core   +1 more source

Design of a voltage-to-time converter and selection of a time-to-digital converter for use in a time-based analog-to-digital converter

, 2015
Analog-to-digital converters (ADC) are becoming essential to the function of ultra-high speed interconnects, while at the same time reduction in supply voltage has negatively impacted the performance of such circuits.
Osheroff, Peter A.
core  

A Multihit Time-to-Digital Converter Architecture on FPGA

, 2009
We present a multihit time-to-digital converter (TDC) architecture implemented in a field-programmable gate array (FPGA) with minimized timing overhead. The TDC circuit provides two-level fine-time interpolation.
Khouas, Abdelhakim, Amiri, Amir Mohammad, Boukadoum, Mounir   +2 more
core