Results 91 to 100 of about 117,069,527 (207)

A Novel Sample-and-Hold-Based Time-to-Digital Converter Architecture

, 2010
In this paper, the design of a Time-to-Digital Converter (TDC) for measuring the Time of Flight (ToF) of a radio pulse is described. The novel idea is based on the adoption of a charge-pump time-to-voltage transducer followed by a Sample-and-Hold ...
CARBONE, Paolo, NAPOLITANO, PASQUALE, ALIMENTI, Federico   +2 more
core   +1 more source

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

IEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun-Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh   +13 more
doaj   +1 more source

Time to digital converter based on a 2-dimensions Vernier architecture

, 2009
A novel 2-dimension Vernier Time to digital converter (TDC) is presented. The proposed architecture reduces drastically the number of delay stage required by linear TDCs minimizing the power consumption and the area of the design.
Luca Vercesi, VERCESI, LUCA, CASTELLO, RINALDO, LISCIDINI, ANTONIO, Antonio Liscidini, Rinaldo Castello   +5 more
core   +1 more source

Implementation of a Pulse-Holding Time-to-Digital Converter on an FPGA

, 2013
In this work, we describe the implementation of a pulse-holding Time-to-Digital Converter (TDC) on a Xilinx Spartan 6 FPGA. We describe the operation of a pulse-holding TDC and we compare it with that of a pulse-shrinking TDC, which is the most similar ...
NAPOLI, ETTORE, Prodomo, Alberto, Alberto Prodomo, Francesco Brandonisio, Ettore Napoli, Brandonisio, Francesco, Kennedy, Michael Peter, Michael Peter Kennedy   +7 more
core   +1 more source

Magnetic-field-to-digital converter using PWM and TDC techniques

, 2006
A high resolution magnetic-field-to-digital converter (MDC) is presented. It is composed of a magnetic-field-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector. This prototype circuit has been
Kuo, C.H.; Chen, S.L.; Liu, S.I.
core  

An Asynchronous Pipelined Time-to-Digital Converter Using Time-Domain Subtraction

, 2018
This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system.
Omer Can Akgun, Akgün, O.C. (author)
core   +1 more source

A Phased-Scaled Vernier Time-to-Digital Converter Architecture with Switchable Coarse/Fine Resolutions, Wide Range and Ultra Low Power Consumption [PDF]

, 2016
A novel phase-scaled Vernier time-to-digital converter (TDC) architecture with a switchable coarse/fine (16ps/2ps) time resolution function is presented to achieve large phase (time) detection range (32.7ns in 14 bits), fine time resolution (2ps ...
Wang, Tuoxin
core   +1 more source

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

Implementation of high-resolution time-to-digital converter in 8-bit microcontrollers

, 2012
This paper will demonstrate how a time-to-digital converter (TDC) with sub-nanosecond resolution can be implemented into an 8-bit microcontroller using so called “direct” methods.
Bengtsson, Lars,, Lars E. Bengtsson
core   +1 more source

A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

, 2014
The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better ...
Perktold, L, Christiansen, J
core   +1 more source