Results 21 to 30 of about 3,473 (197)

A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

open access: yesSensors, 2021
In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources.
Mojtaba Parsakordasiabi   +3 more
doaj   +1 more source

A High-Resolution Single-Photon Arrival-Time Measurement With Self-Antithetic Variance Reduction in Quantum Applications: Theoretical Analysis and Performance Estimation

open access: yesIEEE Transactions on Quantum Engineering, 2022
An almost all-digital time-to-digital converter (TDC) possessing subpicosecond resolutions, scalable dynamic ranges, high linearity, high noise immunity, and moderate conversion rates can be achieved by a random sampling-and-averaging (RSA) approach with
Tony Wu, Tzu-Chien Hsueh
doaj   +1 more source

A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

open access: yesInformation Processing in Agriculture, 2014
Time to digital converter (TDC) is a key block for time-gated single photon avalanche diode (SPAD) arrays for Raman spectroscopy that applicable in the agricultural products and food analysis. In this paper a new dual slope time to digital converter that
Mahdi Rezvanyvardom   +2 more
doaj   +1 more source

A 13-Bit, 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor

open access: yesSensors, 2021
A three-dimensional (3D) image sensor based on Single-Photon Avalanche Diode (SPAD) requires a time-to-digital converter (TDC) with a wide dynamic range and fine resolution for precise depth calculation. In this paper, we propose a novel high-performance
Zunkai Huang   +6 more
doaj   +1 more source

An 8-bit TDC implemented with two nested Johnson counters

open access: yesTecnología en Marcha, 2023
This work presents a Time-to-Digital Converter implemented using two nested Johnson counters and suitable for time-lapse measurement applications. The proposed structure is composed of two 4-bit nested counters, two digital-logic control networks, two ...
Jonathan Santiago-Fernandez   +3 more
doaj   +1 more source

Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

open access: yesApplied Sciences, 2018
This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC ...
Yuan-Ho Chen
doaj   +1 more source

Cross-Talk Issues in Time Measurements

open access: yesIEEE Access, 2021
The enormous diffusion of Time-Mode circuits, in particular Time-to-Digital Converter (TDC) time measurement circuits, and at the same time the dizzying increase in parallel channels required by the most recent applications, for example in the automotive
Nicola Lusardi   +4 more
doaj   +1 more source

Design of Reconfigurable Time-to-Digital Converter Based on Cascaded Time Interpolators for Electrical Impedance Spectroscopy

open access: yesSensors, 2020
This paper presents a reconfigurable time-to-digital converter (TDC) used to quantize the phase of the impedance in electrical impedance spectroscopy (EIS).
Sounghun Shin   +7 more
doaj   +1 more source

A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter [PDF]

open access: yesIEEE transactions on industrial electronics (1982. Print), 2021
Time-to-Digital Converters (TDCs) are major components for the measurements of time intervals. Recent developments in Field-Programmable Gate Array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only possible using ...
Yuanyuan Hua, D. Chitnis
semanticscholar   +1 more source

5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays

open access: yesElectronics, 2023
A tapped delay line (TDL)-based time-to-digital converter (TDC) implemented on an FPGA (Field Programmable Gate Array) is sensitive to nonlinearities because of significant variations in the delay of the delay elements.
Roza Teklehaimanot Siecha   +3 more
semanticscholar   +1 more source

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