Results 31 to 40 of about 3,473 (197)
Time-Mode Signal Quantization for Use in Sigma-Delta Modulators [PDF]
AUT Journal of Electrical Engineering, 2016 The rapid scaling in modern CMOS technology has motivated the researchers to design new analog-to-digital converter (ADC) architectures that can properly work in lower supply voltage.
Mohsen Tamaddon, Mohammad Yavari
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A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification [PDF]
Radioengineering, 2015 This paper investigates a novel cyclic time-to-digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop).
M. Rezvanyvardom, E. Farshidi
doaj
Widening and narrowing of time interval due to single‐event transients in 45 nm vernier‐type TDC
IET Circuits, Devices and Systems, 2017 Single‐event transients (SETs) due to heavy‐ion (HI) strikes adversely affect the electronic circuits in sub‐100 nm regime in radiation environment.
Pasupathy K. Ramaniharan, Bindu Boby
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Time-to-Digital Converter IP-Core for FPGA at State of the Art
IEEE Access, 2021 The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time–Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs,
F. Garzetti +3 more
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A Coarse-Fine Time-to-Digital Converter
ITM Web of Conferences, 2017 A design of time-to-digital converter (TDC) using a coarse-fine conversion scheme is presented. The coarse stage was accomplished by a delay line, and used a loop counter at the end of the delay line to achieve wide dynamic range. The fine stage utilized
Chen Ya-Qian, Meng Li-Ya, Lin Xiao-Gang
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Multi-Channel FPGA Time-to-Digital Converter With 10 ps Bin and 40 ps FWHM
IEEE Transactions on Instrumentation and Measurement, 2022 We present a novel architecture for multi-channel time-to-digital converters (TDCs) to be implemented into low-cost field-programmable gate arrays (FPGAs), achieving 10-ps least significant bit (LSB), 164- $\mu \text{s}$ full-scale range, and good ...
D. Portaluppi +3 more
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IEEE Access, 2021 This paper describes FPGA implementation of a high-order continuous-time multi-stage noise-shaping (MASH) $\Delta \Sigma $ time-to-digital converter (TDC).
Ahmad Mouri Zadeh Khaki +4 more
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Journal of Electrical and Computer Engineering, 2014 We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL).
Chao Chen +4 more
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Applied Sciences, 2022 This paper presents a 19 ps precision and 170 M samples/s time-to-digital converter (TDC) in FPGA. Through the direct count method and tapped delay line method, the coarse count and fine count can be extracted, respectively.
Mengdi Zhang +3 more
semanticscholar +1 more source
Implementation and development of a DAQ system DELILA at ELI-NP [PDF]
EPJ Web of ConferencesThis paper reports the current status of the Data AcQuisition (DAQ) system in ELI-NP, Romania. The DAQ system uses several data-taking electronics modules, CAEN 1730 1725 and 1740 digitizer series, and Mesytec Analog-to-Digital Converter (ADC) and Time ...
Aogaki Sohichiroh, Niculae Stefan
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