Results 141 to 150 of about 702 (169)
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A 20-ps temperature compensated Time-to-Digital Converter (TDC) implemented in FPGA
2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC), 2013This paper presents a temperature compensation design for carry chain based Time-to-Digital Converter (TDC) in FPGA. The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain which shows all TDC channels have the ...
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A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module
Journal of Instrumentation, 2012The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine ...
Büchele, Maximilian +6 more
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A compact Time-to-Digital Converter (TDC) module with 10 ps resolution and less than 1.5% LSB DNL
IEEE Photonics Conference 2012, 2012We present a low-power Time-to-Digital Converter (TDC) module that provides 10 ps timing resolution, DNL better than 1.5% LSB and 160 ns dynamic range within a compact 6 cm × 6 cm × 8 cm housing. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via ...
MARKOVIC, BOJAN +8 more
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A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC
2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), 2023Daniel Junehee Lee +2 more
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2009 4th IEEE Conference on Industrial Electronics and Applications, 2009
This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay ...
null Gao Wu +4 more
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This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay ...
null Gao Wu +4 more
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INTERNATIONAL CONFERENCE ON SMART STRUCTURES AND SYSTEMS - ICSSS'13, 2013
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement.
Mahantesh P. Mattada, Hansraj Guhilot
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We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement.
Mahantesh P. Mattada, Hansraj Guhilot
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Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI), 2022Rodrigo N. Wuerdig +3 more
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2013
In this paper, the Cramér-Rao Lower Bound (CRLB) on the variance of time interval duration estimators is derived for synchronous Time-to-Digital (TDC) converters, based on a coarse counter, keeping into account the effect of noise affecting the TDC clock period. The model has been validated using Montecarlo analysis.
G. De Angelis +2 more
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In this paper, the Cramér-Rao Lower Bound (CRLB) on the variance of time interval duration estimators is derived for synchronous Time-to-Digital (TDC) converters, based on a coarse counter, keeping into account the effect of noise affecting the TDC clock period. The model has been validated using Montecarlo analysis.
G. De Angelis +2 more
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A Novel Flash-Type Time-To-Digital Converters (TDC) Using GDI Technique
2022Jakka Yeshwanth Reddy +4 more
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