Results 121 to 130 of about 118,706,258 (232)

High-resolution time-to-digital converter utilising fractional difference conversion scheme

, 2010
A high-resolution process, voltage and temperature (PVT)-insensitive time-to-digital converter (TDC) is presented, based on a Vernier delay-line, in which the propagation delays in the upper and lower buffer chains are stabilised by two different ...
Xing, Nan, Kim, Suhwan, Shin, W.-Y., Jeong, K.-K., S. Kim, W.-Y. Shin, N. Xing, D.-K. Jeong   +7 more
core   +1 more source

Asynchronous time-to-digital converter [PDF]

, 2017
U sklopu diplomskog rada projektiran je jedan vremensko-digitalni pretvornik te je implementiran na FPGA pločici i prikazani su rezultati mjerenja. Sklop je prošao kroz više promjena dok nisu dobiveni zadovoljavajući rezultati.
Pešerović, Boris
core  

High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA

IEEE Access
In recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs).
Lorenzo Castelvero, Ignacio H. Lopez Grande, Valerio Pruneri   +2 more
doaj   +1 more source

A high-resolution Time-to-Digital Converter based on parallel delay elements

, 2012
This paper presents a flash-type Time to Digital Converter (TDC) based on parallel delay elements in 65-nm CMOS process technology. By using parallel delay elements the conversion resolution of the TDC becomes equal to the difference of delay elements ...
Yao, Chen,, Zheng, Li-Rong,, Jian Chen, Fredrik Jonsson, Chen Yao, Li-Rong Zheng, Chen, Jian,, Jonsson, Fredrik,   +7 more
core   +1 more source

A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout

Applied Sciences
Adder neural networks remove multiplication from convolution, yet their direct L1-distance datapath still requires subtraction, absolute-value generation, and wide accumulation. We address this cost by mapping the online L1 operation to minimum selection
Aoming Zhan, Ye Zhao, Yumei Zhou, Shushan Qiao   +3 more
doaj   +1 more source

Time--to--Digital Converter (TDC)--Based Resonant Compute--in--Memory for INT8 CNNs with Layer--Optimized SRAM Mapping

In recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate~(MAC) is considered a {\textit de facto} unit operation in NNs. By leveraging the inherent parallel processing capabilities of CiM, NNs that require numerous MAC operations can be executed more ...
Challagundla, Dhandeep, Bezzam, Ignatius, Islam, Riadul   +2 more
openaire   +2 more sources

A Programmable Delay Line-Based Measurement Methodology for CMOS LiDAR Receivers. [PDF]

Micromachines (Basel)
Seo B, Lee S, Park S, Park SM.
europepmc   +1 more source

Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS

, 2011
WiMAX (Worldwide Interoperability for Microwave Access) is the emerging wireless technology standard of the near future, which enables high speed packet data access.
Effendrik, P. (author)
core  

Developing the Readout Electronics for a Custom 64 × 64 SPAD Array: From Single-Board Prototyping to FPGA Implementation Toward Stellar Intensity Interferometry. [PDF]

Sensors (Basel)
Quintana Á, González-de-Rivera G, López-Buedo S, Prada F.   +3 more
europepmc   +1 more source

An Energy-Efficient LiDAR Receiver Using Time-to-Voltage Converter and SAR ADC in 180 nm CMOS. [PDF]

Micromachines (Basel)
Seo B, Park SM.
europepmc   +1 more source