Results 121 to 130 of about 1,191 (163)
IEEE Journal of Solid-State Circuits, 2009 This paper describes a time-to-digital converter (TDC) with ~1.2 ps resolution and ~327 mus dynamic range suitable for laser range-finding application for example. The resolution of ~1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive ...
A Mäntyniemi +2 more
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Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC
2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 2023Fei Yuan, Yushi Zhou
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Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI), 2022Bruno Canal +2 more
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A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS
2021 IEEE 14th International Conference on ASIC (ASICON), 2021Yumei Huang
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Two-Dimensions Vernier Time-to-Digital Converter
IEEE Journal of Solid-State Circuits, 2010 A two-dimensions Vernier algorithm applied to a time to digital converter (TDC) is presented. The solution proposed minimizes the length of the delay lines used to perform the digital conversion leading to a better efficiency compared to traditional ...
Antonio Liscidini, R Castello
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2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
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Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
openaire +1 more source
Review on the Evolution of Low-power and Highly-linear Time-to-Digital Converters - TDC
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 2020Time-to-digital converters (TDC) have been widely used in all-digital phase-locked loops (ADPLL). However, the TDC non-linearity and resolution have negatively impacted the ADPLL performance. A better integration between the TDC and ADPLL would improve the performance of the ADPLL, with a minimum increase in power consumption.
Lesley Ferreira +5 more
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NORCHIP 2010, 2010
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
A Mäntyniemi, Juha Kostamovaara
exaly +2 more sources
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
A Mäntyniemi, Juha Kostamovaara
exaly +2 more sources
Quantization noise improvement of Time to Digital converter (TDC) for ADPLL
2009 IEEE International Symposium on Circuits and Systems, 2009A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒ c , based on a input reference frequency ...
Jawaharlal Tangudu +8 more
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