Results 131 to 140 of about 1,191 (163)
Some of the next articles are maybe not open access.
2011 IEEE International Instrumentation and Measurement Technology Conference, 2011
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
A Mäntyniemi, Juha Kostamovaara
exaly +4 more sources
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
A Mäntyniemi, Juha Kostamovaara
exaly +4 more sources
Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS
2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver.
Popong Effendrik +4 more
openaire +1 more source
A High-Resolution Time-Based Resistance-to-Digital Converter with TDC and Counter
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018This paper presents a high resolution time-based resistance-to-digital converter for amp-less high-precision sensor application. In order to solve the trade-off between resolution and bandwidth, a time-to-digital converter (TDC) is combined with a resistance-controlled-oscillator.
Shuya Nakagawa +2 more
openaire +1 more source
A synthesizable Time to Digital Converter (TDC) with MIMO spatial oversampling method
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015A 7 ps/LSB, 0.02 mm2 and 3.9 mW@50MHz Time to Digital Converter architecture with novel MIMO spatial oversampling method is proposed as part of an effort to implement an all-digital PLL (ADPLL) by replacing the phase frequency detector in phase locked loops (PLL).
Yalçin Balcioglu, Günhan Dündar
openaire +1 more source
Time-to-digital converter (TDC) based on startable ring oscillators and successive approximation
2014 NORCHIP, 2014This paper presents a time-to-digital converter (TDC) architecture based on startable ring oscillators (SRO) and the cyclic time domain successive approximation principle. A ring oscillator is first used as a coarse interpolator within the cycle of the reference clock, after which the ring oscillator is used as a phase memory for the time domain ...
Antti Mäntyniemi, Juha Kostamovaara
openaire +1 more source
High resolution distributed time-to-digital converter (TDC) in a White Rabbit network
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2014Abstract The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km2 areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray ...
Weibin Pan +4 more
openaire +1 more source
2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2012
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
A Mäntyniemi, Juha Kostamovaara
exaly +2 more sources
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
A Mäntyniemi, Juha Kostamovaara
exaly +2 more sources
IEEE Transactions on Nuclear Science, 2014
This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain.
Weibin Pan, Guanghua Gong, Jianmin Li
exaly +2 more sources
This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain.
Weibin Pan, Guanghua Gong, Jianmin Li
exaly +2 more sources
Design and Experiment of Ultrasonic Anemometer Using TDC-GP2 Time-to-Digital Converter
Key Engineering Materials, 2014An ultrasonic anemometer using TDC-GP2 high-accuracy time measuring chip is studied in this paper, the design of software and hardware parts and principle of flying time measurement using TDC-GP2 chip are also discussed in detail. Under this scheme, a prototype has been fabricated, with simpler circuit architecture.
Han Yu Du, Ming Qin
openaire +1 more source
A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module
Journal of Instrumentation, 2012The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine ...
Büchele, Maximilian +6 more
openaire +2 more sources