Results 131 to 140 of about 702 (169)

Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 2023
Fei Yuan, Yushi Zhou
exaly   +2 more sources

A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS

2021 IEEE 14th International Conference on ASIC (ASICON), 2021
Yumei Huang
exaly   +2 more sources

Review on the Evolution of Low-power and Highly-linear Time-to-Digital Converters - TDC

2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 2020
Time-to-digital converters (TDC) have been widely used in all-digital phase-locked loops (ADPLL). However, the TDC non-linearity and resolution have negatively impacted the ADPLL performance. A better integration between the TDC and ADPLL would improve the performance of the ADPLL, with a minimum increase in power consumption.
Lesley Ferreira, Mateus Moreira, Barbara Souza, Sandro B. Ferreira, Filipe D. Baumgratz, Sergio Bampi   +5 more
openaire   +1 more source

Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

2009 IEEE International Symposium on Circuits and Systems, 2009
A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒ c , based on a input reference frequency ...
Jawaharlal Tangudu, Sarma Gunturi, Saket Jalan, Jayawardan Janardhanan, Raghu Ganesan, Debapriya Sahu, Khurram Waheed, John L. Wallberg, Robert Bogdan Staszewski   +8 more
openaire   +1 more source

Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS

2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011
WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver.
Popong Effendrik, Wenlong Jiang, Marcel van de Gevel, Frank Verwaal, Robert Bogdan Staszewski   +4 more
openaire   +1 more source

A High-Resolution Time-Based Resistance-to-Digital Converter with TDC and Counter

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018
This paper presents a high resolution time-based resistance-to-digital converter for amp-less high-precision sensor application. In order to solve the trade-off between resolution and bandwidth, a time-to-digital converter (TDC) is combined with a resistance-controlled-oscillator.
Shuya Nakagawa, Kaito Horikoshi, Hiroki Ishikuro   +2 more
openaire   +1 more source

A synthesizable Time to Digital Converter (TDC) with MIMO spatial oversampling method

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015
A 7 ps/LSB, 0.02 mm2 and 3.9 mW@50MHz Time to Digital Converter architecture with novel MIMO spatial oversampling method is proposed as part of an effort to implement an all-digital PLL (ADPLL) by replacing the phase frequency detector in phase locked loops (PLL).
Yalçin Balcioglu, Günhan Dündar
openaire   +1 more source

Time-to-digital converter (TDC) based on startable ring oscillators and successive approximation

2014 NORCHIP, 2014
This paper presents a time-to-digital converter (TDC) architecture based on startable ring oscillators (SRO) and the cyclic time domain successive approximation principle. A ring oscillator is first used as a coarse interpolator within the cycle of the reference clock, after which the ring oscillator is used as a phase memory for the time domain ...
Antti Mäntyniemi, Juha Kostamovaara
openaire   +1 more source

Design and Experiment of Ultrasonic Anemometer Using TDC-GP2 Time-to-Digital Converter

Key Engineering Materials, 2014
An ultrasonic anemometer using TDC-GP2 high-accuracy time measuring chip is studied in this paper, the design of software and hardware parts and principle of flying time measurement using TDC-GP2 chip are also discussed in detail. Under this scheme, a prototype has been fabricated, with simpler circuit architecture.
Han Yu Du, Ming Qin
openaire   +1 more source

Design and Implementation of a Digital Phase-Locked Loop (DPLL) with Vernier Time-to-Digital Converter (TDC) for Dynamic Frequency Selection

2024 Global Conference on Communications and Information Technologies (GCCIT)
Rajath Vasudevamurthy
exaly   +2 more sources