Results 171 to 180 of about 10,650 (234)
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2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2012
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
S. Alahdab +2 more
semanticscholar +2 more sources
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
S. Alahdab +2 more
semanticscholar +2 more sources
A 20-ps temperature compensated Time-to-Digital Converter (TDC) implemented in FPGA
2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC), 2013This paper presents a temperature compensation design for carry chain based Time-to-Digital Converter (TDC) in FPGA. The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain which shows all TDC channels have the ...
Weibin Pan +3 more
semanticscholar +2 more sources
High resolution distributed time-to-digital converter (TDC) in a White Rabbit network
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2014Abstract The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km2 areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray ...
Weibin Pan +4 more
semanticscholar +2 more sources
IEEE Transactions on Nuclear Science, 2014
This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain.
Weibin Pan, G. Gong, Jianmin Li
semanticscholar +2 more sources
This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain.
Weibin Pan, G. Gong, Jianmin Li
semanticscholar +2 more sources
INTERNATIONAL CONFERENCE ON SMART STRUCTURES AND SYSTEMS - ICSSS'13, 2013
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement.
Mahantesh P. Mattada, H. Guhilot
semanticscholar +2 more sources
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement.
Mahantesh P. Mattada, H. Guhilot
semanticscholar +2 more sources
2009 4th IEEE Conference on Industrial Electronics and Applications, 2009
This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay ...
Gao Wu +4 more
semanticscholar +2 more sources
This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay ...
Gao Wu +4 more
semanticscholar +2 more sources
A High-Resolution Time-Based Resistance-to-Digital Converter with TDC and Counter
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018This paper presents a high resolution time-based resistance-to-digital converter for amp-less high-precision sensor application. In order to solve the trade-off between resolution and bandwidth, a time-to-digital converter (TDC) is combined with a ...
S. Nakagawa +2 more
semanticscholar +2 more sources
2011 IEEE Recent Advances in Intelligent Computational Systems, 2011
We present an area efficient Time to Digital Converter (TDC) yielding a high resolution of nearly 10ps. The TDC architecture reported in this paper comprises of coarse measurement using system clock and two controllable oscillators for fine resolution measurement.
Mahantesh P Mattad, H. Guhilot, R. Kamat
semanticscholar +2 more sources
We present an area efficient Time to Digital Converter (TDC) yielding a high resolution of nearly 10ps. The TDC architecture reported in this paper comprises of coarse measurement using system clock and two controllable oscillators for fine resolution measurement.
Mahantesh P Mattad, H. Guhilot, R. Kamat
semanticscholar +2 more sources
IEEE Transactions on Nuclear Science, 2012
The latest delay chain-based FPGA TDCs can achieve resolutions around 10 ps. At such high levels of accuracy, delay chains become very sensitive to parasitic electromagnetic perturbations, including power supply voltage, temperature, and current surge. This paper describes how common-mode fast perturbation can deteriorate the spectra and make the root ...
Jiayue Qi, H. Gong, Yinong Liu
semanticscholar +2 more sources
The latest delay chain-based FPGA TDCs can achieve resolutions around 10 ps. At such high levels of accuracy, delay chains become very sensitive to parasitic electromagnetic perturbations, including power supply voltage, temperature, and current surge. This paper describes how common-mode fast perturbation can deteriorate the spectra and make the root ...
Jiayue Qi, H. Gong, Yinong Liu
semanticscholar +2 more sources
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2012
Abstract The paper presents and compares FPGA implementations of Time-to-Digital Converters (TDC) developed in the framework of the XNAP project, an international collaboration building Avalanche Photo Diode based area X-ray detectors. We are revisiting and presenting updated results achieved with recent components of two different TDC architectures ...
C. Hervé, J. Cerrai, T. L. Caër
semanticscholar +2 more sources
Abstract The paper presents and compares FPGA implementations of Time-to-Digital Converters (TDC) developed in the framework of the XNAP project, an international collaboration building Avalanche Photo Diode based area X-ray detectors. We are revisiting and presenting updated results achieved with recent components of two different TDC architectures ...
C. Hervé, J. Cerrai, T. L. Caër
semanticscholar +2 more sources