Results 21 to 30 of about 12,217,467 (150)
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories [PDF]
, 2012 In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage ...
C. Zambelli +19 more
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Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory
IEEE Access, 2021 In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss.
Fei Wang +3 more
doaj +1 more source
EDACs and test integration strategies for NAND flash memories [PDF]
, 2010 Mission-critical applications usually presents several critical issues: the required level of dependability of the whole mission always implies to address different and contrasting dimensions and to evaluate the tradeoffs among them. A mass-memory device
Piazza, R. +9 more
core +1 more source
FLARE: A design environment for FLASH-based space applications [PDF]
, 2009 Designing a mass-memory device (i.e., a solid-state recorder) is one of the typical issues of mission-critical space system applications. Flash-memories could be used for this goal: a huge number of parameters and trade-offs need to be explored.
Stefano Di Carlo +8 more
core +1 more source
IEEE Access, 2023 When designing 3D V-NAND technologies with a gate induced drain leakage (GIDL) assisted erase scheme, many experiments must be conducted to determine the optimal GIDL design targets to achieve fast erase performance and secure yield characteristics ...
Yohan Kim, Soyoung Kim
doaj +1 more source
Micromachines, 2021 In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better ...
Woo-Jin Jung, Jun-Young Park
doaj +1 more source
Micromachines, 2023 Electrical characteristics with various program temperatures (TPGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the TPGM up to 120 °C and the read temperature (TREAD) at 30 °C are used to analyze the
Ukju An +6 more
doaj +1 more source
Cryogenic Storage Memory with High‐Speed, Low‐Power, and Long‐Retention Performance
Advanced Electronic Materials, 2023 Cryogenic‐computing draws attention due to its variety of applications such as cloud‐computing, aerospace electronics, and quantum computing. Low temperature (e.g., 77 K) enables higher switching speed, improved reliability, and suppressed noise ...
Jae Hur +5 more
doaj +1 more source
Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference
Micromachines, 2021 Minimizing the variation in threshold voltage (Vt) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently.
Su-in Yi, Jungsik Kim
doaj +1 more source
, 2022 International audienceBulk bitwise operations, i.e., bitwise operations on large bit vectors, are prevalent in a wide range of important application domains, including databases, graph processing, genome analysis, cryptography, and hyper-dimensional ...
Park, Jisung +8 more
core +3 more sources