Results 11 to 20 of about 8,846,054 (209)
Automated Metrology on the Verticality of Cross-Sectioned Channel Hole at V-NAND with Over 200 Layers by Transmission Electron Microscope [PDF]
International Symposium for Testing and Failure Analysis, 2021 Abstract This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells.
Dong-yeob Kim +2 more
openaire +2 more sources
Wordline Input Bias Scheme for Neural Network Implementation in 3D-NAND Flash [PDF]
BiomimeticsIn this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs).
Hwiho Hwang +3 more
doaj +2 more sources
Dual-Doped Cylindrical Bit-Line Pad for High-Efficiency Bulk Erase in V-NAND Flash
IEEE AccessWe propose a novel dual-doped cylindrical bit-line (DDC-BL) pad structure for vertical NAND (V-NAND) flash memory to enable efficient bulk erase operation through direct hole injection.
Choasub Kim +4 more
doaj +2 more sources
Electrical Screening Method of V-NAND Flash Channel Hole Bending Defects [PDF]
International Symposium for Testing and Failure Analysis, 2021 Abstract This paper presents a novel approach for detecting channel hole bending (ChB) defects in vertical NAND flash memory. Such defects are the result of etching process inconsistencies and contribute to data loss and device failure by inducing leakage current between adjacent channel holes.
Dooyeun Jung +10 more
openaire +1 more source
Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN MIS-HEMTs IC Platform
IEEE Journal of the Electron Devices Society, 2023 In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility ...
Yuhao Zhu +8 more
doaj +1 more source
Nanomaterials, 2022 As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the
Xinyue Yu +6 more
doaj +1 more source
Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash
Micromachines, 2023 The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang +4 more
doaj +1 more source
Nanomaterials, 2022 A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation.
Kihoon Nam +10 more
doaj +1 more source
Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories
IEEE Journal of the Electron Devices Society, 2021 The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells.
Jun Gyu Lee +4 more
doaj +1 more source
Nanomaterials, 2023 Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture.
Hongsheng Hu +8 more
doaj +1 more source