Results 21 to 30 of about 3,668 (177)
Dual-Doped Cylindrical Bit-Line Pad for High-Efficiency Bulk Erase in V-NAND Flash
IEEE AccessWe propose a novel dual-doped cylindrical bit-line (DDC-BL) pad structure for vertical NAND (V-NAND) flash memory to enable efficient bulk erase operation through direct hole injection.
Choasub Kim +4 more
doaj +2 more sources
Retention Characteristics and DMP Efficiency in V-NAND With Dimple Structure
IEEE Journal of the Electron Devices SocietyIn this paper, we analyze the retention characteristics of vertical NAND(V-NAND) with dimpled (convex and concave) structures considering the impact of adjacent cell states.
Seongwoo Kim +3 more
doaj +2 more sources
Architectural and Integration Options for 3D NAND Flash Memories
Computers, 2017 Nowadays, NAND Flash technology is everywhere, since it is the core of the code and data storage in mobile and embedded applications; moreover, its market share is exploding with Solid-State-Drives (SSDs), which are replacing Hard Disk Drives (HDDs) in ...
Rino Micheloni +2 more
exaly +3 more sources
Wordline Input Bias Scheme for Neural Network Implementation in 3D-NAND Flash [PDF]
BiomimeticsIn this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs).
Hwiho Hwang +3 more
doaj +2 more sources
Electrical Screening Method of V-NAND Flash Channel Hole Bending Defects [PDF]
International Symposium for Testing and Failure Analysis, 2021 Abstract This paper presents a novel approach for detecting channel hole bending (ChB) defects in vertical NAND flash memory. Such defects are the result of etching process inconsistencies and contribute to data loss and device failure by inducing leakage current between adjacent channel holes.
Dooyeun Jung +10 more
openaire +1 more source
Machine Learning Based Optimization Technique for High-Capacity V-NAND Flash Memory [PDF]
International Symposium for Testing and Failure Analysis, 2021 Abstract In the NAND flash manufacturing process, thousands of internal electronic fuses (eFuse) are tuned in order to optimize performance and validity. In this paper, we propose a machine learning optimization technique that uses deep learning (DL) and genetic algorithms (GA) to automatically tune eFuse values.
Jisuk Kim +14 more
openaire +1 more source
Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN MIS-HEMTs IC Platform
IEEE Journal of the Electron Devices Society, 2023 In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility ...
Yuhao Zhu +8 more
doaj +1 more source
Nanomaterials, 2022 As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the
Xinyue Yu +6 more
doaj +1 more source
Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash
Micromachines, 2023 The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang +4 more
doaj +1 more source
Nanomaterials, 2022 A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation.
Kihoon Nam +10 more
doaj +1 more source