Results 21 to 30 of about 4,326 (205)

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors

open access: yesSensors, 2023
Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling,
Hanshui Fan   +6 more
doaj   +1 more source

Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory

open access: yesMicromachines, 2023
The instability in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated.
Donghyun Go   +6 more
doaj   +1 more source

Automated Metrology on the Verticality of Cross-Sectioned Channel Hole at V-NAND with Over 200 Layers by Transmission Electron Microscope [PDF]

open access: yesInternational Symposium for Testing and Failure Analysis, 2021
Abstract This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells.
Dong-yeob Kim   +2 more
openaire   +1 more source

Match‐line control unit for power and delay reduction in hybrid CAM

open access: yesIET Circuits, Devices and Systems, 2021
Content addressable memory (CAM) is a hardware search engine utilised for accelerating translation and table look‐up in network routers and data processing systems.
Sheikh Wasmir Hussain   +3 more
doaj   +1 more source

Investigation of Poly Silicon Channel Variation in Vertical 3D NAND Flash Memory

open access: yesIEEE Access, 2022
Since the most of three dimensional (3D) NAND devices’ channel is composed of polysilicon grain, the actual 3D NAND channel has a wave-shaped channel, not uniform shape.
Inyoung Lee   +3 more
doaj   +1 more source

Controlling the beam angle spread of carbon implantation for improvement of bin map defect in V-NAND flash memory

open access: yesMemories - Materials, Devices, Circuits and Systems, 2023
As the shrinkage of devices accelerates and the vertical layers increase, beam angle spread of carbon ion implantation (C IIP) for the silicon selective epitaxial growth (Si-SEG) areas in V-NAND is one of the most critical parameters related with bin map defects.
Gui-Fu Yang   +6 more
openaire   +2 more sources

Low-voltage solution-processed Cuprous thiocyanate Thin-Film transistors with NAND logic function

open access: yesResults in Physics, 2023
Coprous thiocyanate (CuSCN)-based thin-film transistors (TFTs) by solution-processed chitosan electrolyte are fabricated on glass substrates. Such TFTs show a low operation voltage of −2.0 V due to the large specific gate capacitance of 7.65 μF/cm2 ...
Liuhui Lei   +7 more
doaj   +1 more source

Robust mean absolute deviation problems on networks with linear vertex weights [PDF]

open access: yes, 2013
This article deals with incorporating the mean absolute deviation objective function in several robust single facility location models on networks with dynamic evolution of node weights, which are modeled by means of linear functions of a parameter ...
López de los Mozos Martín, María Cruz   +2 more
core   +1 more source

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

open access: yesIEEE Access, 2021
In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss.
Fei Wang   +3 more
doaj   +1 more source

800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

open access: yesIEEE Access, 2013
A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm2 HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations.
Peter Gillingham   +7 more
doaj   +1 more source

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