Results 31 to 40 of about 10,230,919 (179)
Single Event Effects in 3D NAND Flash Memory Cells with Replacement Gate Technology [PDF]
We studied the heavy-ion single event effect response of 3D NAND Flash memory cells with charge-trap based replacement gate technology. Error cross sections, threshold voltage shifts, and underlying mechanisms are discussed.
Gerardin S. +6 more
core +1 more source
Low-voltage solution-processed Cuprous thiocyanate Thin-Film transistors with NAND logic function
Coprous thiocyanate (CuSCN)-based thin-film transistors (TFTs) by solution-processed chitosan electrolyte are fabricated on glass substrates. Such TFTs show a low operation voltage of −2.0 V due to the large specific gate capacitance of 7.65 μF/cm2 ...
Liuhui Lei +7 more
doaj +1 more source
A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm2 HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations.
Peter Gillingham +7 more
doaj +1 more source
We present a behavioral compact model and its implementation for low-voltage pentacene-based organic thin film transistors (OTFTs) using industry standard BSIM4 (Berkeley Short-channel IGFET Model) in LTspice platform.
Nihat Akkan, Mustafa Altun, Herman Sedef
doaj +1 more source
Ferroelectric tunnel junction devices based on epitaxial undoped ferroelectric HfO2 films demonstrate stable switching endurance of over 106 switching cycles, low write voltages of ±3 V, 16 measured resistance states, and neuromorphic capability.
Markus Hellenbrand +13 more
wiley +1 more source
Electrical characteristics with various program temperatures (TPGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the TPGM up to 120 °C and the read temperature (TREAD) at 30 °C are used to analyze the
Ukju An +6 more
doaj +1 more source
Compute-in-memory (CIM) has emerged as a promising solution to mitigate the data movement bottleneck in von Neumann architectures. While vertical NAND (V-NAND) flash memory has been explored for CIM, its structural constraints, including pass-bias ...
Jonghyun Ko +9 more
doaj +1 more source
Nand gate architectures for memory decoder [PDF]
This paper presents some nand gate design styles which when used in decoder reduces energy consumption and delay. Basically conventional, nor style nand, source coupled nand is discussed.
Shivkaran Jain +3 more
core +1 more source
Digitally Printed Eco‐Friendly Electronic Devices
Fabrication of electronics using eco‐friendly materials through digital printing routes is a promising strategy for improving life cycle sustainability and reducing the environmental impacts of conventional manufacturing. This review highlights state‐of‐the‐art eco‐friendly materials, green ink formulations, various resource‐efficient digital printing ...
Nitheesh M. Nair +5 more
wiley +1 more source
Material Coupling in Hybrid Neuromorphic Devices: From Fundamentals to System‐Level Applications
Hybrid neuromorphic devices utilize heterointerfaces between emerging semiconductors, where charge transfer and trapping, ion or defect modulation, and photogating are translated into synaptic functions. This paper discusses coupling strategies that tailor interfacial electronic and ionic properties in organic semiconductors, metal oxides, two ...
Minsu So +5 more
wiley +1 more source

