Results 51 to 60 of about 10,230,919 (179)
[[abstract]]Embedded NAND-type read-only-memory (NAND-ROM) provides large-capacity, high-reliability, on-chip non-volatile storage. However, NAND-ROM suffers from code-dependent read noises and cannot survive at low supply voltages (VDDs).
M.-F. Chang
core +1 more source
Implicit-OR tiling of deoxyribozymes: Construction of molecular scale OR, NAND and four-input logic gates [PDF]
We recently reported the first complete set of molecular-scale logic gates based on deoxyribozymes. Here we report how we tile these logic gates and construct new logic elements: OR, NAND, and the first element with four inputs (i1^i5)V(i2^i6). Tiling of
Stojanović Milan N. +2 more
doaj +1 more source
Inhibited Channel Potential of 3D NAND Flash Memory String According to Transient Time
The channel potential of natural local self-boosting (NLSB) effects in 16-layer 3D NAND flash memory was analyzed according to transient time. After a program pulse was applied to the selected word line (WL) of the inhibited string channel, the channel ...
Taeyoung Cho, Hyunju Kim, Myounggon Kang
doaj +1 more source
Wafer‐Scale 3D Integration for High‐Density Multi‐Valued Neuromorphic Logic
Wafer‐scale 3D vertically integrated multi‐valued logic (MVL) circuits are realized by monolithically integrating a Te/IGZO heterojunction FET with an engineered Te pull‐up FET. Heterointerface‐mediated transport and optimized current matching enable stable ternary operation, while vertical stacking reduces circuit footprint and interconnect complexity,
Chang‐Hyeon Kim +5 more
wiley +1 more source
A dual‐randomness hardware platform is demonstrated by integrating PUF and TRNG functionalities into mixed‐ZGO nanoclusters. By leveraging spatial and temporal stochasticity, the mixed‐ZGO NCs device enables both unique identification and random signal generation.
Seungme Kang +6 more
wiley +1 more source
Model‐Inversion‐Resistant Physical Unclonable Neural Network Using Vertical NAND Flash Memory
The growing use of neural networks in privacy‐sensitive applications necessitates architectures that inherently protect both data and model integrity.
Sung‐Ho Park +8 more
doaj +1 more source
GeSbSe selector‐only memory devices are investigated through physical and electrical analyses to reveal opposite trap‐state evolution pathways governing reliability degradation. Endurance cycling drives Se migration, transitioning traps from deep to shallow states.
Byung Jun Lee +3 more
wiley +1 more source
Re‐Thinking Electronic Circuit Design Through Emerging Reconfigurable Field Effect Transistors
Graphical illustration of reconfigurable field effect transistor (RFET) operation modes, including n‐type, p‐type, and ambipolar transport, as well as their areas of application discussed in this review: digital circuit design, analog circuit design, post‐Shannon computing, and sensing. ABSTRACT Reconfigurable field‐effect transistors, short RFETs, are
Jens Trommer +19 more
wiley +1 more source
Random telegraph noise (RTN) shifts the threshold voltage (Vt) of 3D NAND flash memory cells, making it a key factor of the device malfunction. The aim of this study is to predict the distribution of RTN induced ${\mathrm { V}}_{\mathrm { t}}$ shift in
Eunseok Oh, Hyungcheol Shin
doaj +1 more source
NAND Flash Memory Organization and Operations
NAND flash memories are well known for their uncomplicated structure, low cost, and high capacity. Their typical characteristics include architecture, sequential reading, and high density.
Kuchta, Radek +2 more
core +1 more source

