Results 61 to 70 of about 3,697 (183)

A Low-Power BL Path Design for NAND Flash Based on an Existing NAND Interface

Journal of Low Power Electronics and Applications
This paper is an extended version of a previously reported conference paper regarding a low-power design for NAND Flash. As the number of bits per NAND Flash die increases with cost scaling, the IO data path speed increases to minimize the page access ...
Hikaru Makino, Toru Tanzawa
doaj   +1 more source

Monotonic transition based forward body bias for dual threshold voltage low power embedded processors [PDF]

Advances in Radio Science, 2006
Dual threshold voltage and forward body bias techniques are effective ways to optimally balance the standby leakage power and performance. In this paper, we propose a novel fine-grained forward body biasing scheme for monotonic static logic circuits.
S. Jayapal, Y. Manoli
doaj  

Exploiting Ferroelectric and Spintronic Dynamics for Neural Network Computation

Advanced Intelligent Systems, EarlyView.
Ferroelectric and spintronic devices, relying on the control of polarization and magnetization, offer intrinsically fast, durable, energy‐efficient, and low‐latency building blocks for analog in‐memory computing. The hysteretic dynamics of an order parameter are leveraged to provide nonvolatile, multistate memory and nonlinear switching. Brain‐inspired
Dashiell Harrison, Kevin Nadaud, Josquin Harrison, Guillaume F. Nataf, Laura Bégon‐Lours   +4 more
wiley   +1 more source

Ising Solver Using Vertical NAND Flash Memory

Advanced Intelligent Systems, EarlyView.
Commercial V‐NAND flash memory is repurposed as a discrete‐time Ising solver by exploiting in‐memory current summation and read‐voltage‐controlled intrinsic noise. The system implements Hopfield neural‐network updates with simulated‐annealing‐like behavior, solving max‐cut problems with high accuracy and energy efficiency while using mass‐produced ...
Sung‐Ho Park, Yeongheon Yang, Jong‐Won Back, Jiseong Im, Ryun‐Han Koo, Jonghyun Ko, Dongseok Kwon, Jong‐Ho Lee   +7 more
wiley   +1 more source

Atomic Layer-Deposited HfAlOx-Based RRAM with Low Operating Voltage for Computing In-Memory Applications

Nanoscale Research Letters, 2019
With Moore’s law closing to its physical limit, traditional von Neumann architecture is facing a challenge. It is expected that the computing in-memory architecture-based resistive random access memory (RRAM) could be a potential candidate to overcome ...
Zhen-Yu He, Tian-Yu Wang, Lin Chen, Hao Zhu, Qing-Qing Sun, Shi-Jin Ding, David Wei Zhang   +6 more
doaj   +1 more source

An unusual titanosaur axis from the Upper Cretaceous of Brazil and its significance for sauropod anatomy and systematics

The Anatomical Record, EarlyView.
Abstract The Upper Cretaceous São José do Rio Preto Formation (Bauru Group, southeastern Brazil) has yielded a fragmentary but taxonomically diverse record of titanosaur sauropods, although elements from cervical series remain scarce. Here, we describe a nearly complete sauropod axis from the Vila Ventura Paleontological Area, representing an uncommon ...
Bruno A. Navarro, Jeffrey A. Wilson Mantilla, Jhonata H. A. Martins, Fabiano V. Iori, Leonardo S. Paschoa, Alberto B. Carvalho, Joseli M. Piranha, Hussam Zaher   +7 more
wiley   +1 more source

Digital Transformation for Sustainable Development of SMEs: A Systematic Review of ‘How We Know,’ ‘What We Know’ and Research Agenda

Business Strategy and the Environment, EarlyView.
ABSTRACT Small‐ and medium‐sized enterprises (SMEs) are expected to contribute more significantly to the sustainability agenda. Digital transformation (DT) has the potential to enable SMEs to fulfil their sustainable development goals. However, SMEs encounter unique challenges in leveraging DT for sustainability due to their size, limited resources and
Phuc G. Le, Duyen Chu, Thomas Domboka, Hien Nguyen   +3 more
wiley   +1 more source

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory With Separated Source-Line

IEEE Access
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj   +1 more source

Analog Low-Voltage Current-Mode Implementation of Digital Logic Gates

Active and Passive Electronic Components, 2003
In this letter a new technique is introduced for implementing the basic logic functions using analog current-mode techniques. By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic ...
Muhammad Taher Abuelma'atti
doaj   +1 more source

A Co‐Designed Implicit‐Reset Path PFD and Current Mismatch Compensated CP Enabling Sub‐0.5% Mismatch and Dead Zone‐Free for Low‐Spur PLLs

International Journal of Circuit Theory and Applications, EarlyView.
A co‐designed implicit‐reset phase‐frequency detector (PFD) and nonlinear amplifier‐assisted charge pump (CP) achieve dead zone‐free operation from 10 MHz to 4.7 GHz with < 0.5% current mismatch without calibration, enabling −80 dBc of reference spur and 0.50 ps of RMS jitter in a 180 nm of CMOS PLL.
A. Ghaemnia, Jincheng Yang, Xiaojiong Fei, G. Zhang   +3 more
wiley   +1 more source