Results 41 to 50 of about 4,326 (205)
Nano ConvergenceCompute-in-memory (CIM) has emerged as a promising solution to mitigate the data movement bottleneck in von Neumann architectures. While vertical NAND (V-NAND) flash memory has been explored for CIM, its structural constraints, including pass-bias ...
Jonghyun Ko +9 more
doaj +1 more source
Implicit-OR tiling of deoxyribozymes: Construction of molecular scale OR, NAND and four-input logic gates [PDF]
Journal of the Serbian Chemical Society, 2003 We recently reported the first complete set of molecular-scale logic gates based on deoxyribozymes. Here we report how we tile these logic gates and construct new logic elements: OR, NAND, and the first element with four inputs (i1^i5)V(i2^i6). Tiling of
Stojanović Milan N. +2 more
doaj +1 more source
Advanced Functional Materials, EarlyView.Ferroelectric tunnel junction devices based on epitaxial undoped ferroelectric HfO2 films demonstrate stable switching endurance of over 106 switching cycles, low write voltages of ±3 V, 16 measured resistance states, and neuromorphic capability.
Markus Hellenbrand +13 more
wiley +1 more source
Inhibited Channel Potential of 3D NAND Flash Memory String According to Transient Time
Applied Sciences, 2023 The channel potential of natural local self-boosting (NLSB) effects in 16-layer 3D NAND flash memory was analyzed according to transient time. After a program pulse was applied to the selected word line (WL) of the inhibited string channel, the channel ...
Taeyoung Cho, Hyunju Kim, Myounggon Kang
doaj +1 more source
Atomic Layer Deposition in Transistors and Monolithic 3D Integration
Advanced Functional Materials, EarlyView.Transistors are fundamental building blocks of modern electronics. This review summarizes recent progress in atomic layer deposition (ALD) for the synthesis of two‐dimensional (2D) metal oxides and transition‐metal dichalcogenides (TMDCs), with particular emphasis on their enabling role in monolithic three‐dimensional (M3D) integration for next ...
Yue Liu +5 more
wiley +1 more source
CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE [PDF]
, 2015 This project report focuses on the multiple-value logic (MVL) or commonly known as ternary logic gates by using carbon nanotube (CNT) FETs devices (CNTFETs).
Ee, Poey Guan
core
Evolution of Materials and Device Stacks for HfO2‐Based Ferroelectric Memories
Advanced Materials Interfaces, EarlyView.This review summarizes engineering strategies for HfO2 based ferroelectric memories with focus on FeCAP and FeFET structures. It describes how dopant design, stress effects, and interface engineering improve the bulk ferroelectric response. It further discusses how channel engineering supports reliable memory characteristics and scalable integration ...
Eunjin Kim, Jiyong Woo
wiley +1 more source
A 0.821-ratio purely combinatorial algorithm for maximum k-vertex cover in bipartite graphs [PDF]
, 2016 We study the polynomial time approximation of the max k-vertex cover problem in bipartite graphs and propose a purely combinatorial algorithm that beats the only such known algorithm, namely the greedy approach. We present a computer-assisted analysis of
A Badanidiyuru +7 more
core +1 more source
Advanced Materials Technologies, EarlyView.Transducers convert physical signals into electrical and optical representations, yet each mechanism is bounded by intrinsic trade‐offs across bandwidth, sensitivity, speed, and energy. This review maps transduction mechanisms across physical scale and frequency, showing how heterogeneous integration and multiphysics co‐design transform isolated ...
Aolei Xu +8 more
wiley +1 more source
Streaming Complexity of Approximating Max 2CSP and Max Acyclic Subgraph [PDF]
, 2017 We study the complexity of estimating the optimum value of a Boolean 2CSP (arity two constraint satisfaction problem) in the single-pass streaming setting, where the algorithm is presented the constraints in an arbitrary order.
Guruswami, Venkatesan +2 more
core +1 more source