Results 41 to 50 of about 3,668 (177)
Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory
IEEE Access, 2021 In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss.
Fei Wang +3 more
doaj +1 more source
IEEE Access, 2013 A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm2 HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations.
Peter Gillingham +7 more
doaj +1 more source
Engineering Science and Technology, an International Journal, 2023 We present a behavioral compact model and its implementation for low-voltage pentacene-based organic thin film transistors (OTFTs) using industry standard BSIM4 (Berkeley Short-channel IGFET Model) in LTspice platform.
Nihat Akkan, Mustafa Altun, Herman Sedef
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Micromachines, 2023 Electrical characteristics with various program temperatures (TPGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the TPGM up to 120 °C and the read temperature (TREAD) at 30 °C are used to analyze the
Ukju An +6 more
doaj +1 more source
Advanced Engineering Materials, EarlyView.A reconfigurable logic‐in‐memory cell composed of triple‐gated feedback field‐effect transistors implements multiple combinational logic functions within a single configuration. By utilizing program gates as dynamic input terminals, the proposed cell performs full adder, full subtractor, 2‐to‐1 multiplexer, and 4‐to‐2 encoder operations without ...
Minhyeok Seol +5 more
wiley +1 more source
Micromachines, 2021 In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better ...
Woo-Jin Jung, Jun-Young Park
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Advanced Functional Materials, EarlyView.Edible electronics needs integrated logic circuits for computation and control. This work presents a potentially edible printed chitosan‐gated transistor with a design optimized for integration in circuits. Its implementation in integrated logic gates and circuits operating at low voltage (0.7 V) is demonstrated, as well as the compatibility with an ...
Giulia Coco +8 more
wiley +1 more source
Implicit-OR tiling of deoxyribozymes: Construction of molecular scale OR, NAND and four-input logic gates [PDF]
Journal of the Serbian Chemical Society, 2003 We recently reported the first complete set of molecular-scale logic gates based on deoxyribozymes. Here we report how we tile these logic gates and construct new logic elements: OR, NAND, and the first element with four inputs (i1^i5)V(i2^i6). Tiling of
Stojanović Milan N. +2 more
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Advanced Functional Materials, EarlyView.Oxygen‐tunnel (OT) indium tin oxide (ITO) vertical channel transistors (VCTs) enable reliable, high‐density gain‐cell memory for monolithic 3D integration. A sandwiched SiN/SiO2/SiN OT stack selectively regulates oxygen transport, suppressing parasitic electrode oxidation while stabilizing channel oxygen vacancies, thereby suppressing carrier injection
Hyeonho Gu +17 more
wiley +1 more source
Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory
IEEE Journal of the Electron Devices SocietyThis article investigates the impact of band-to-band tunneling (BTBT) occurring in the charge trap layer (CTL) of vertical NAND (V−NAND) flash memory under excessive erasure conditions and aggressive program operation. Strong local electric fields
Seongwoo Kim +3 more
doaj +1 more source