Results 11 to 20 of about 10,230,919 (179)

Triple‐Level Content‐Addressable Vertical NAND Flash Memory

Advanced Science
Content‐addressable memory (CAM) enables massively parallel search by directly comparing input data with stored entries, offering a powerful paradigm for accelerating data‐intensive tasks. Here, we present a triple‐level content‐addressable vertical NAND
Sung‐Ho Park, Jiseong Im, Yeongheon Yang, Ryun‐Han Koo, Jonghyun Ko, Mingyun Oh, Dongbeen Shin, Gyuweon Jung, Jong‐Ho Lee   +8 more
doaj   +3 more sources

Numerical Study on the Laser Annealing of Silicon Used in Advanced V-NAND Device

Materials, 2022
Laser melt annealing of amorphous silicon (a-Si) and subsequent recrystallization of a-Si are essential processes for successfully implementing vertical NAND (V-NAND) flash memory devices developed based on the cell-over-periphery (COP) structure. The aim of this study was to develop the numerical model for the laser melting process of a-Si used in V ...
Yeong-Il Son, Joonghan Shin
openaire   +3 more sources

Concealable physical unclonable functions using vertical NAND flash memory

Nature Communications
Physical Unclonable Functions (PUFs) can address the demand for enhanced hardware security. Vertical NAND (V-NAND) flash memory is the most commercialized non-volatile memory.
Sung-Ho Park, Ryun-Han Koo, Yeongheon Yang, Jiseong Im, Jonghyun Ko, Jong-Ho Lee   +5 more
doaj   +2 more sources

Ising Solver Using Vertical NAND Flash Memory

Advanced Intelligent Systems
Combinatorial optimization problems are notoriously hard for conventional computers to solve efficiently. While quantum and analog hardware have been explored to tackle these problems, they often face challenges such as high power use, complexity, or ...
Sung‐Ho Park, Yeongheon Yang, Jong‐Won Back, Jiseong Im, Ryun‐Han Koo, Jonghyun Ko, Dongseok Kwon, Jong‐Ho Lee   +7 more
doaj   +2 more sources

Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider V_th Window in 3D NAND Flash Using a Machine-Learning Method

Nanomaterials, 2022
A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation.
Kihoon Nam, Chanyang Park, Jun-Sik Yoon, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Ho-Jung Kang, Min-Sang Park, Jaesung Sim, Hyun-Chul Choi, Rock-Hyun Baek   +10 more
doaj   +2 more sources

A Low-Power BL Path Design for NAND Flash Based on an Existing NAND Interface

Journal of Low Power Electronics and Applications
This paper is an extended version of a previously reported conference paper regarding a low-power design for NAND Flash. As the number of bits per NAND Flash die increases with cost scaling, the IO data path speed increases to minimize the page access ...
Hikaru Makino, Toru Tanzawa
doaj   +2 more sources

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

Micromachines, 2023
The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang, Bao Zhang, Qi Wang, Lei Jin, Zhiliang Xia   +4 more
doaj   +1 more source

Automated Metrology on the Verticality of Cross-Sectioned Channel Hole at V-NAND with Over 200 Layers by Transmission Electron Microscope [PDF]

International Symposium for Testing and Failure Analysis, 2021
Abstract This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells.
Dong-yeob Kim, Jong-ick Son, Christopher H Kang   +2 more
openaire   +1 more source

Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories

IEEE Journal of the Electron Devices Society, 2021
The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells.
Jun Gyu Lee, Woo Je Jung, Jae Hyeon Park, Keon-Ho Yoo, Tae Whan Kim   +4 more
doaj   +1 more source

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories [PDF]

, 2012
In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage ...
C. Zambelli, P. Olivo, Indaco, Marco, Olivo P., M. Indaco, BERTOZZI, Davide, Zambelli, C., Di Carlo, Stefano, Olivo, P., Bertozzi D., P. Prinetto, D. Bertozzi, M. Fabiano, ZAMBELLI, Cristian, OLIVO, Piero, Fabiano, Michele, Prinetto, Paolo Ernesto, S. Di Carlo, Bertozzi, D., Zambelli C.   +19 more
core   +1 more source