Results 11 to 20 of about 4,326 (205)

Model‐Inversion‐Resistant Physical Unclonable Neural Network Using Vertical NAND Flash Memory

Advanced Science
The growing use of neural networks in privacy‐sensitive applications necessitates architectures that inherently protect both data and model integrity.
Sung‐Ho Park, Ryun‐Han Koo, Jonghyun Ko, Jiseong Im, Yeongheon Yang, Mingyun Oh, Dongbeen Shin, Gyuweon Jung, Jong‐Ho Lee   +8 more
doaj   +2 more sources

Machine Learning Based Optimization Technique for High-Capacity V-NAND Flash Memory [PDF]

International Symposium for Testing and Failure Analysis, 2021
Abstract In the NAND flash manufacturing process, thousands of internal electronic fuses (eFuse) are tuned in order to optimize performance and validity. In this paper, we propose a machine learning optimization technique that uses deep learning (DL) and genetic algorithms (GA) to automatically tune eFuse values.
Jisuk Kim, Earl Kim, Daehyeon Lee, Taeheon Lee, Daesik Ham, Miju Yang, Wanha Hwang, Jaeyoung Kim, Sangyong Yoon, Youngwook Jeong, Eunkyoung Kim, Ki-Whan Song, Jai Hyuk Song, Myungsuk Kim, Woo Young Choi   +14 more
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Electrical Screening Method of V-NAND Flash Channel Hole Bending Defects [PDF]

International Symposium for Testing and Failure Analysis, 2021
Abstract This paper presents a novel approach for detecting channel hole bending (ChB) defects in vertical NAND flash memory. Such defects are the result of etching process inconsistencies and contribute to data loss and device failure by inducing leakage current between adjacent channel holes.
Dooyeun Jung, Youngha Choi, Jae In Lee, Bu-il Nam, Ki-Young Dong, Bohchang Kim, Eunkyoung Kim, Ki-Whan Song, Jai Hyuk Song, Myungsuk Kim, Woo Young Choi   +10 more
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Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN MIS-HEMTs IC Platform

IEEE Journal of the Electron Devices Society, 2023
In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility ...
Yuhao Zhu, Fan Li, Miao Cui, Zhicheng Fang, Ang Li, Dongyi Yang, Yinchao Zhao, Huiqing Wen, Wen Liu   +8 more
doaj   +1 more source

3D NAND Flash Memory Based on Double-Layer NC-Si Floating Gate with High Density of Multilevel Storage

Nanomaterials, 2022
As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the
Xinyue Yu, Zhongyuan Ma, Zixiao Shen, Wei Li, Kunji Chen, Jun Xu, Ling Xu   +6 more
doaj   +1 more source

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

Micromachines, 2023
The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang, Bao Zhang, Qi Wang, Lei Jin, Zhiliang Xia   +4 more
doaj   +1 more source

Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider V_th Window in 3D NAND Flash Using a Machine-Learning Method

Nanomaterials, 2022
A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation.
Kihoon Nam, Chanyang Park, Jun-Sik Yoon, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Ho-Jung Kang, Min-Sang Park, Jaesung Sim, Hyun-Chul Choi, Rock-Hyun Baek   +10 more
doaj   +1 more source

Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories

IEEE Journal of the Electron Devices Society, 2021
The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells.
Jun Gyu Lee, Woo Je Jung, Jae Hyeon Park, Keon-Ho Yoo, Tae Whan Kim   +4 more
doaj   +1 more source

Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer

Nanomaterials, 2023
Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture.
Hongsheng Hu, Zhongyuan Ma, Xinyue Yu, Tong Chen, Chengfeng Zhou, Wei Li, Kunji Chen, Jun Xu, Ling Xu   +8 more
doaj   +1 more source

Adaptive Pulse Programming Scheme for Improving the V_th Distribution and Program Performance in 3D NAND Flash Memory

IEEE Journal of the Electron Devices Society, 2021
For triple-level or quad-level 3D NAND flash memory, narrowing the Vth distribution of each state without influencing page program performance is one of the challenges.
Zhichao Du, Shuang Li, Yu Wang, Xiang Fu, Fei Liu, Qi Wang, Zongliang Huo   +6 more
doaj   +1 more source