Results 151 to 160 of about 4,190 (193)

Atmospheric Neutron Soft Errors in 3-D NAND Flash Memories

IEEE Transactions on Nuclear Science, 2019
The sensitivity of vertical-channel 3-D NAND flash memories to wide-energy spectrum neutrons was investigated. The effects of neutron exposure on a 3-D floating gate (FG) cells were studied in terms of threshold voltage shifts and raw bit error rates. The neutron failure rates obtained in the accelerated tests were extrapolated to field conditions at ...
M. Bagatin, S. Gerardin, A. Paccagnella, S. Beltrami, C. Cazzaniga, C. D. Frost   +5 more
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Optimization of Performance and Reliability in 3D NAND Flash Memory

IEEE Electron Device Letters, 2020
3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO2 (O1) layer thickness near poly Si channel in the tunnel layer based on SiO2/SiOxNy/SiO2 structure.
Yingjie Ouyang, Zhiliang Xia, Tao Yang, Dandan Shi, Wenxi Zhou, Zongliang Huo   +5 more
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3D VG-Type NAND Flash Memories

2016
The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack.
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FPGA-based reliability testing and analysis for 3D NAND flash memory

Microelectronics Reliability, 2020
Abstract In this article, we described a FPGA-based NAND flash memory hardware and software collaborative design experimental platform. Our novel experimental platform implements timing control and error feature extraction of NAND flash memory, equipped with a computer software based on LabVIEW.
Debao Wei, Zhelong Piao, Hua Feng, Liyan Qiao, Xiyuan Peng   +4 more
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A cell current compensation scheme for 3D NAND FLASH memory

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015
The 3D NAND, so-called vertical NAND has cell Vt degradation especially in low temperature, and it affects cell Vt distribution and shift when NAND operates. To solve this problem, the temperature compensation scheme by ATS(Analog Temp Sensor) using CTAT circuit has proposed.
SungWook Choi, KyuTae Park, Marco Passerini, HeeJoung Park, DoYoung Kim, ChiHyun Kim, KunWoo Park, JinWoong Kim   +7 more
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Error Generation for 3D NAND Flash Memory

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022
Weihua Liu, Fei Wu, Songmiao Meng, Xiang Chen, Changsheng Xie   +4 more
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3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array

IEICE Transactions on Electronics, 2009
We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F 2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process.
Yoon KIM, Seongjae CHO, Gil Sung LEE, Il Han PARK, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK   +6 more
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7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016
A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations.
Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo   +60 more
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Advanced Architectures for 3D NAND Flash Memories with Vertical Channel

2016
One of the key metrics to benchmark different 3D architectures is the storage density, which is here indicated with Bit_Density. Given a specific Flash memory die, this density is defined as the ratio between the storage capacity of the die, Die_Capacity, and its silicon area, Die_Size. In this chapter we present some of the most advanced architectures
Luca Crippa, Rino Micheloni
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Multilevel In-Memory-Searching in 3D NAND-Flash Memory

Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials, 2022
Po Hao Tseng, Feng Ming Lee, Yung Chun Li, Yu Hsuan Lin, Chih Wei Hu, Chih Chang Hsieh, Ming Hsiu Lee, Kuang Yeu Hsieh, Keh Chung Wang, Chih Yuan Lu   +9 more
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