Results 161 to 170 of about 802 (202)

Error Generation for 3D NAND Flash Memory

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022
Weihua Liu, Fei Wu 0005, Songmiao Meng, Xiang Chen 0028, Changsheng Xie 0001   +4 more
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Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory

2019 IEEE International Reliability Physics Symposium (IRPS), 2019
3D NAND flash memory has entered dynamically into the space of enterprise server and storage systems, offering significantly higher capacity and better endurance than the latest 2D technology node. Moreover, the advancements in vertical stacking, cell design and program/read algorithms, have also enabled TLC 3D NAND flash with enterprise-level ...
Nikolaos Papandreou, Haralampos Pozidis, Thomas P. Parnell, Nikolas Ioannou, Roman A. Pletka, Sasa Tomic, Patrick Breen, Gary A. Tressler, Aaron Fry, Timothy Fisher   +9 more
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Impact of etch angles on cell characteristics in 3D NAND flash memory

Microelectronics Journal, 2018
Abstract We investigated the impact of etch angles on cell characteristics of 3D NAND flash memory structures. The cell characteristics were extracted from simulations with an empirical etch profile, which was analyzed through comparisons to completely vertical conditions.
Young-Taek Oh, Kyu-Beom Kim, Sang-Hoon Shin, Hahng Sim, Nguyen Van Toan, Takahito Ono, Yunheub Song   +6 more
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Vertical-channel stacked array (VCSTAR) for 3D NAND flash memory

2011 International Semiconductor Device Research Symposium (ISDRS), 2011
Abstract A novel three-dimensional (3D) NAND flash memory, VCSTAR (Vertical-Channel STacked ARray), is investigated. The proposed device is a vertical channel structure having stacked word-lines to achieve high memory density without shrinking cell channel length.
Se Hwan Park, Yoon Kim, Wandong Kim, Joo Yun Seo, Byung-Gook Park   +4 more
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3D VG-Type NAND Flash Memories

2016
The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack.
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Trends and Future Challenges of 3D NAND Flash Memory

2023 IEEE International Memory Workshop (IMW), 2023
Sun Il Shim, Jaehoon Jang 0002, Jaihyuk Song   +2 more
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Modeling and optimization of Array Leakage in 3D NAND Flash Memory

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2018
In this paper, complicated array leakage current of three-dimensional (3D) vertical channel NAND flash memory has been investigated and optimized. Monte Carlo simulation results show the design of channel hole layout, process variation of channel hole critical dimension are identified to the leakage issue.
Yu-jie Song, Zhi-liang Xia, Wen-yu Hua, Fandong Liu, Zong-liang Huo   +4 more
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Multilevel In-Memory-Searching in 3D NAND-Flash Memory

Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials, 2022
Po Hao Tseng, Feng Ming Lee, Yung Chun Li, Yu Hsuan Lin, Chih Wei Hu, Chih Chang Hsieh, Ming Hsiu Lee, Kuang Yeu Hsieh, Keh Chung Wang, Chih Yuan Lu   +9 more
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Layer-to-Layer Endurance Variation of 3D NAND Flash Memory

2022 IEEE International Reliability Physics Symposium (IRPS), 2022
Md Raquibuzzaman, Md. Mehedi Hasan, Aleksandar Milenkovic, Biswajit Ray   +3 more
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Introduction to 3D NAND Flash Memories

2022
Rino Micheloni, Luca Crippa, Cristian Zambelli   +2 more
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