Results 21 to 30 of about 1,100 (152)

Tunneling Transistors Based on MoS₂/MoTe₂ Van der Waals Heterostructures

IEEE Journal of the Electron Devices Society, 2018
2-D transition metal dichalcogenides (TMDs) are promising materials for CMOS application due to their ultrathin channel with excellent electrostatic control.
Yashwanth Balaji, Quentin Smets, Cesar Javier Lockhart De La Rosa, Anh Khoa Augustin Lu, Daniele Chiappe, Tarun Agarwal, Dennis H. C. Lin, Cedric Huyghebaert, Iuliana Radu, Dan Mocuta, Guido Groeseneken   +10 more
doaj   +1 more source

Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

Crystals, 2021
The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network.
Zhihua Zhu, Zhaonian Yang, Xiaomei Fan, Yingtao Zhang, Juin Jei Liou, Wenbing Fan   +5 more
doaj   +1 more source

Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs [PDF]

, 2017
The characteristic performance of n-type and p-type inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode, bulk Germanium FinFET device with 3-nm gate length (LG) are demonstrated by using 3-D quantum transport device simulation.
Asenov, Asen, Georgiev, Vihar P., Jhan, Yi-Ruei, Kurniawan, Erry Dwi, Lee, Jaehyun, Lema, Fikru-Adamu, Lin, Yu-Ru, Sadi, Toufik, Soundarapandian, Karuppasamy Pandian, Thirunavukkarasu, Vasanthan, Wu, Yung-Chun, Yang, Shang-Yi   +11 more
core   +1 more source

Insights into tunnel FET-based charge pumps and rectifiers for energy harvesting applications [PDF]

, 2017
In this paper, the electrical characteristics of tunnel field-effect transistor (TFET) devices are explored for energy harvesting front-end circuits with ultralow power consumption.
Moll Echeto, Francisco de Borja, Nunes Cavalheiro, David Manuel, Valtchev, Stanimir   +2 more
core   +2 more sources

Bilayer tunneling field effect transistor with oxide-semiconductor and group-IV semiconductor hetero junction: Simulation analysis of electrical characteristics

AIP Advances, 2019
Operation mechanisms and electrical characteristics of tunneling field-effect transistors (TFETs) employing a hetero tunneling junction by utilizing an n-type oxide-semiconductor (OS) and a p-type group-IV-semiconductor are comprehensibly analyzed.
Kimihiko Kato, Hiroaki Matsui, Hitoshi Tabata, Mitsuru Takenaka, Shinichi Takagi   +4 more
doaj   +1 more source

Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs

IEEE Access, 2017
In this paper, we have performed a comprehensive analysis of the gate-induced drain leakage (GIDL) in emerging nanotube (NT) and nanowire (NW) FET architectures.
Shubham Sahay, Mamidala Jagadesh Kumar
doaj   +1 more source

Synergy of Electrostatic and Chemical Doping to Improve the Performance of Junctionless Carbon Nanotube Tunneling Field-Effect Transistors: Ultrascaling, Energy-Efficiency, and High Switching Performance

Nanomaterials, 2022
The low on-current and direct source-to-drain tunneling (DSDT) issues are the main drawbacks in the ultrascaled tunneling field-effect transistors based on carbon nanotube and ribbons.
Khalil Tamersit, Abdellah Kouzou, Hocine Bourouba, Ralph Kennel, Mohamed Abdelrahem   +4 more
doaj   +1 more source

A quantitative study of the relationship between the oxide charge trapping over the drain extension and the off-state drain leakage current [PDF]

, 2004
In this letter, we report an approach to quantitative study of the relationship between the oxide charge trapping over the drain extension due to electrical stress and the off-state drain leakage current.
Ang, CH, Chen, TP, Fung, S, Huang, J, Manju, S   +4 more
core   +1 more source

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Applied Sciences, 2018
Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage.
Hsin-Hui Hu, Yan-Wei Zeng, Kun-Ming Chen
doaj   +1 more source

Low-κ Extension Doping for High-Performance Carbon Nanotube Transistors: Toward High-Speed, Energy-Efficient Electronics. [PDF]

Adv Sci (Weinh)
This study presents the first experimental demonstration of a low‐κ extension doping strategy for CNT MOSFETs using stacked SiOx/AlFx layers. The proposed approach minimizes parasitic capacitance and reduces total resistance by 85%, significantly enhancing device performance. These findings establish a scalable, ultra‐thin doping method for high‐speed,
Chiu HY, Chou CH, Wu GZ, Huang HY, Liu BH, Kei CC, Chien CH.   +6 more
europepmc   +2 more sources