Results 21 to 30 of about 573 (171)
In this paper, we have performed a comprehensive analysis of the gate-induced drain leakage (GIDL) in emerging nanotube (NT) and nanowire (NW) FET architectures.
Shubham Sahay, Mamidala Jagadesh Kumar
doaj +1 more source
The low on-current and direct source-to-drain tunneling (DSDT) issues are the main drawbacks in the ultrascaled tunneling field-effect transistors based on carbon nanotube and ribbons.
Khalil Tamersit +4 more
doaj +1 more source
Compact and energy-efficient Synapse and Neurons are essential to realize the full potential of neuromorphic computing. In addition, a low variability is indeed needed for neurons in Deep neural networks for higher accuracy. Further, process (P), voltage
Sharma, Anand +7 more
core +1 more source
The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM).
Wei Li +4 more
doaj +1 more source
Comparative performance analysis of different gate structure engineering on double gate tunnel FET
Through band-to-band tunneling, Tunnel Field Effect Transistors (TFETs) reduce leakage and subthreshold swing, giving them an advantage over MOSFET. However, ambipolar conduction and low ON state current are problems with traditional TFET.
Sudha Subhalaxmi Muduli +3 more
doaj +1 more source
Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage.
Hsin-Hui Hu, Yan-Wei Zeng, Kun-Ming Chen
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Monolayer Transition Metal Dichalcogenide Channel-Based Tunnel Transistor
We investigate the gate controlled direct band-to-band tunneling (BTBT) current in monolayer transition-metal dichalcogenide (MX2) channel-based tunnel field effect transistor (TFET).
Ram Krishna Ghosh, Santanu Mahapatra
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Single-Charge Tunneling in Codoped Silicon Nanodevices
Silicon (Si) nano-electronics is advancing towards the end of the Moore’s Law, as gate lengths of just a few nanometers have been already reported in state-of-the-art transistors.
Daniel Moraru +7 more
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TCAD Simulation Study of ESD Behavior of InGaAs/InP Heterojunction Tunnel FETs
For the first time, we investigated the electrostatic discharge (ESD) behavior of an InGaAs/InP heterojunction tunneling field effect transistor (HTFET). The device structure in this study has a high on-state current without extra process steps.
Zhihua Zhu +5 more
doaj +1 more source
This article presents a new line tunneling dominating metal–semiconductor contact-induced SiGe–Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given
Jyi-Tsong Lin, Shao-Cheng Weng
doaj +1 more source

