Results 51 to 60 of about 573 (171)

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

IEEE Journal of the Electron Devices Society, 2015
Guided by the Wentzel-Kramers-Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified.
Qing-Tai Zhao, Simon Richter, Christian Schulte-Braucks, Lars Knoll, Sebastian Blaeser, Gia Vinh Luong, Stefan Trellenkamp, Anna Schafer, Andreas Tiedemann, Jean-Michel Hartmann, Konstantin Bourdelle, Siegfried Mantl   +11 more
doaj   +1 more source

Organic Transistor‐Based Neuromorphic Electronics and Their Recent Applications

Small Methods, Volume 10, Issue 7, 6 April 2026.
This review highlights recent progress in organic neuromorphic electronics, showing how organic semiconductors enable synaptic and neuronal functions with low power, mechanical flexibility, and biocompatibility. By bridging materials, devices, and systems, organic platforms are accelerating brain‐inspired computing toward applications in artificial ...
Ziru Wang, Feng Yan
wiley   +1 more source

Theoretical evaluation of maximum electric field approximation of direct band-to-band tunneling Kane model for low bandgap semiconductors

, 2016
The two-band Kane model has been popularly used to calculate the band-to-band tunneling (BTBT) current in tunnel field-effect transistor (TFET) which is currently considered as a promising candidate for low power applications.
Chun-Hsing Shih, Nguyễn, Đăng Chiến, Phù, Chí Hòa, Nguyen Hong Minh, Le Hong Nhung, Dương, Thị Thanh Hiên   +5 more
core   +1 more source

Steep Switching Characteristics of L-Shaped Tunnel FET With Doping Engineering

IEEE Journal of the Electron Devices Society, 2021
In this work, a L-shaped tunnel FET (TFET), which has the dominant tunneling current in the normal direction to the gate, is introduced with the doping engineering and its electrical characteristics are analyzed using TCAD device simulations.
Hyun Woo Kim, Daewoong Kwon
doaj   +1 more source

Room-temperature spin transport through band-to-band tunneling at semiconductor p-n junctions [PDF]

Oki K., Ueda S., Usami T., et al. Room-temperature spin transport through band-to-band tunneling at semiconductor p-n junctions. Physical Review Applied 23, L051005 (2025); https://doi.org/10.1103/physrevapplied.23.l051005.We report electrical spin ...
Yamamoto, K., Hamaya, K., Ueda, S., Usami, T., Kikuoka, S., Fujii, S., Oki, K., Sawano, K.   +7 more
core   +1 more source

Interface Segmentation Approach (InSeAp) on TCAD for Statistical Analysis of Interface Trap Spatial Variations in TFETs

IEEE Access
This work proposes a methodology to conduct statistical analyses of variation in spatial location and concentration of gate oxide/ semiconductor interface traps taking the example of a p-i-n silicon-on-insulator (SOI) tunnelling field-effect transistor ...
Anirudh Koteshwar, Shanidul Hoque, Deepjyoti Deb, Rupam Goswami   +3 more
doaj   +1 more source

Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study

IEEE Access, 2020
The leakage mechanisms of inefficient volume depletion and lateral band to band tunneling (L-BTBT) restrict the scaling of SOI-junctionless (JL) FETs. Therefore, in this article, we investigate the scalability of the SOI-JLFETs by incorporating a ground ...
Aakash Kumar Jain, Mamidala Jagadesh Kumar   +1 more
doaj   +1 more source

Design Space and Variability Analysis of SOI MOSFET for Ultra-Low Power Band-to-Band Tunneling Neurons

, 2023
Large spiking neural networks (SNNs) require ultra-low power and low variability hardware for neuromorphic computing applications. Recently, a band-to-band tunneling-based (BTBT) integrator, enabling sub-kHz operation of neurons with area and energy ...
Sonawane, Jay, Lashkare, Sandip, Singh, Ajay Kumar, Patil, Shubham, Kadam, Abhishek, Deshpande, Veeresh, Ganguly, Udayan   +6 more
core  

Electrically Binary and Ternary Convertible CMOS Inverter and Logic Gate Using Complementary Field‐Effect Transistors Based on Vertically Stacked MoS2/WSe2 n‐/p‐ Field‐Effect Transistors

Advanced Functional Materials, Volume 36, Issue 1, 2 January 2026.
In this work, a reconfigurable T‐CMOS inverter based on vertically stacked MoS2 and WSe2 MOSFETs with a gate‐tunable MoS2 resistor, enabling stable ternary logic, is demonstrated. The T‐CMOS inverter supports electrical switching between ternary and binary modes and is further extended to implement ternary NAND (NMIN) and NOR (NMAX) logic gates ...
Changwook Lee, Dongyoung Kim, Eunyeong Yang, Jiwon Ma, Kibum Kang, Jiwon Chang   +5 more
wiley   +1 more source

In-Built N⁺ Pocket Electrically Doped Tunnel FET With Improved DC and Analog/RF Performance

Micromachines, 2020
In this paper, we present an in-built N+ pocket electrically doped tunnel FET (ED-TFET) based on the polarity bias concept that enhances the DC and analog/RF performance. The proposed device begins with a MOSFET like structure (n-p-n) with a control gate
Jun Li, Ying Liu, Su-fen Wei, Chan Shan
doaj   +1 more source