Results 51 to 60 of about 360 (132)
IEEE AccessThis work proposes a methodology to conduct statistical analyses of variation in spatial location and concentration of gate oxide/ semiconductor interface traps taking the example of a p-i-n silicon-on-insulator (SOI) tunnelling field-effect transistor ...
Anirudh Koteshwar +3 more
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Advanced Materials Technologies, Volume 11, Issue 7, 6 April 2026.The 4R principle—Resilience, Repairability, Recyclability, and Renewability—enables sustainable liquid‐metal transistors. LM materials provide stretchable, damage‐tolerant architectures, allow rapid circuit repair, permit full material recovery through dissolution, and support renewable fabrication cycles, forming a closed‐loop pathway toward ...
Elahe Parvini, Abdollah Hajalilou
wiley +1 more source
In-Built N+ Pocket Electrically Doped Tunnel FET With Improved DC and Analog/RF Performance
Micromachines, 2020 In this paper, we present an in-built N+ pocket electrically doped tunnel FET (ED-TFET) based on the polarity bias concept that enhances the DC and analog/RF performance. The proposed device begins with a MOSFET like structure (n-p-n) with a control gate
Jun Li, Ying Liu, Su-fen Wei, Chan Shan
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Organic Transistor‐Based Neuromorphic Electronics and Their Recent Applications
Small Methods, Volume 10, Issue 7, 6 April 2026.This review highlights recent progress in organic neuromorphic electronics, showing how organic semiconductors enable synaptic and neuronal functions with low power, mechanical flexibility, and biocompatibility. By bridging materials, devices, and systems, organic platforms are accelerating brain‐inspired computing toward applications in artificial ...
Ziru Wang, Feng Yan
wiley +1 more source
Effects of the Channel Length on the Nanoscale Field Effect Diode Performance [PDF]
Journal of Optoelectronical Nanostructures, 2018 Field Effect Diode (FED)s are interesting device in providing the higherON-state current and lower OFF–state current in comparison with SOI-MOSFETstructures with similar dimensions. The impact of channel length and band-to-bandtunneling (BTBT) on the OFF-
arash rezaei +2 more
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SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
Applied SciencesThree-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase ...
Dohyun Kim, Wonbo Shim
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Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors
IEEE Journal of the Electron Devices Society, 2020 Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control.
Shelly Garg, Sneh Saurabh
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Advanced Functional Materials, Volume 36, Issue 1, 2 January 2026.In this work, a reconfigurable T‐CMOS inverter based on vertically stacked MoS2 and WSe2 MOSFETs with a gate‐tunable MoS2 resistor, enabling stable ternary logic, is demonstrated. The T‐CMOS inverter supports electrical switching between ternary and binary modes and is further extended to implement ternary NAND (NMIN) and NOR (NMAX) logic gates ...
Changwook Lee +5 more
wiley +1 more source
Scientific Reports, 2017 Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature.
Wolfgang A. Vitale +10 more
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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2020 The tunnel field-effect transistor (TFET) is a promising solution for high energy-efficient circuits. Based on the band-to-band tunneling (BTBT) condition, fast switching characteristic with a steep subthreshold swing (SS) in the ultralow-voltage ...
Jo-Han Hung +5 more
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