Results 131 to 140 of about 3,848,813 (157)

Curing of Hot-Carrier Induced Damage by Gate-Induced Drain Leakage Current in Gate-All-Around FETs

IEEE Electron Device Letters, 2019
Gate oxide aging in a gate-all-around (GAA) FET fabricated on a bulk substrate was successfully cured by gate-induced drain leakage (GIDL) current. High level of GIDL current flows during the off-state cures the gate oxide aging by hot-carrier injection (
Yang-Kyu Choi, Chang-Hoon Jeon, Jun-Young Park   +2 more
exaly   +2 more sources

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Simulation of amplified gate-induced-drain-leakage (GIDL) in short-channel SOI MOSFETs

Proceedings of International Workshop on Numerical Modeling of processes and Devices for Integrated Circuits: NUPAD V, 2002
Amplification of gate-induced-drain-leakage current has been reported for short channel MOS-transistors on SOI substrate. Here, we show that this effect is reproduced consistently by 2D-device simulation when a band-to-band tunneling model is included.
A. von Schwerin, W. Bergner, K. Jacobs
openaire   +2 more sources

Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors

IEEE Transactions on Electron Devices, 2015
In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies.
Yuancheng Yang
exaly   +2 more sources

A capacitor-less 1T-DRAM cell with vertical surrounding gates using gate-induced drain-leakage (GIDL) current

2008 IEEE Silicon Nanoelectronics Workshop, 2008
A capacitor-less one-transistor DRAM cell with surrounding gate MOSFET with vertical channel (SGVC) using gate-induced drain leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact ionization current, the write operation with GIDL current provides high sensing margin owing to higher ...
Han Ki Chung, Hoon Jeong, Yeun Seung Lee, Jae Young Song, Jong Pil Kim, Sang Wan Kim, Jae Hyun Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park   +9 more
openaire   +1 more source

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005
We demonstrate that for aggressively scaled FinFETs, with 2nm HfO 2 and TiN metal gate (i.e., workfunction close to midgap), several parasitic leakage mechanisms that impact the off-state current become dominant. We provide a detailed characterization of these mechanisms as well as design guidelines for eliminating them by careful junction dopant ...
T. Hoffmann, A. Dixit, K. De Meyer, M. Jurczak, S. Biesemans, G. Doornbos, I. Ferain, N. Collaert, P. Zimmerman, M. Goodwin, R. Rooyackers, A. Kottantharayil, Y. Yim   +12 more
openaire   +1 more source

Design of SOI FinFET on 32nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Solid-State Electronics, 2009
Recently, minimizing the standby power is considered as a critical issue in high-density, mobile CMOS technology. One of the major sources of the leakage current in off-state of ultra-small MOSFET is gate-induced drain leakage (GIDL) which is mainly composed of inter-band and trap-assisted tunneling.
null Seongjae Cho, null Jung Hoon Lee, S. O'uchi, K. Endo, M. Masahara, null Byung-Gook Park   +5 more
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Novel design to improve band to band tunneling and gate induced drain leakages (GIDL) in cylindrical gate all around (GAA) MOSFET

Microsystem Technologies, 2017
In this paper a cylindrical Dual Metal (DM) Dielectric Engineered (DE) Gate All Around (GAA) MOSFET has been proposed to resolve a big issue of Gate Inducted Drain leakage (GIDL) current in cylindrical Gate All Around (GAA) MOSFET to enhance the device reliability. Dual Metal Dielectric Engineered Gate All Around (DMDEGAA) MOSFET has been compared with
Sonam Rewari, Vandana Nath, Subhasis Haldar, S. S. Deswal, R. S. Gupta   +4 more
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A new model for the description of gate voltage and temperature dependence of gate induced drain leakage (GIDL) in the low electric field region [DRAMs]

IEEE Transactions on Electron Devices, 2000
Gate induced drain leakage (GIDL) is frequently described by band-to-band tunneling. This mechanism is insensitive to temperature and occurs only under strong electric fields. Under the condition of small electric fields, however, GIDL exhibits a strong dependence on temperature, which is due to trap-assisted generation of electron hole pairs.
M. Rosar, B. Leroy, G. Schweeger
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A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory

IEEE International Electron Devices Meeting 2003, 2004
A capacitorless 1T DRAM cell using gate-induced drain leakage (GIRL) current for write operation was demonstrated for the first time. Compared with the conventional write operation with impact ionization current, write operation with GIDL current provides low-power and high-speed operation. The capacitorless 1T-DRAM is the most promising technology for
E. Yoshida, T. Tanaka
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The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta

IEEE Electron Device Letters, 1992
An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 mu m SOI devices.
J. Chen, F. Assaderaghi, P.-K. Ko, C. Hu
openaire   +1 more source