Results 131 to 140 of about 311 (157)

A new model for the description of gate voltage and temperature dependence of gate induced drain leakage (GIDL) in the low electric field region [DRAMs]

IEEE Transactions on Electron Devices, 2000
Gate induced drain leakage (GIDL) is frequently described by band-to-band tunneling. This mechanism is insensitive to temperature and occurs only under strong electric fields. Under the condition of small electric fields, however, GIDL exhibits a strong dependence on temperature, which is due to trap-assisted generation of electron hole pairs.
M. Rosar, B. Leroy, G. Schweeger
exaly   +2 more sources

Impact of Process-Induced Inclined Sidewalls on Gate-Induced Drain Leakage (GIDL) Current of Nanowire GAA MOSFETs

IEEE Transactions on Electron Devices, 2022
Ashraf Maniyar, P S T N Srinivas, Pramod Kumar Tiwari   +2 more
exaly   +2 more sources

Macaroni Channel-Nanowire-Field Effect Transistor (MC-NW-FET) for Gate Induced Drain Leakage (GIDL) Reduction Application

2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 2022
Aapurva Kaul, Sonam Rewari, Deva Nand
exaly   +2 more sources

Curing of Hot-Carrier Induced Damage by Gate-Induced Drain Leakage Current in Gate-All-Around FETs

IEEE Electron Device Letters, 2019
Gate oxide aging in a gate-all-around (GAA) FET fabricated on a bulk substrate was successfully cured by gate-induced drain leakage (GIDL) current. High level of GIDL current flows during the off-state cures the gate oxide aging by hot-carrier injection (
Jun-Young Park, Yang-Kyu Choi, Chang-Hoon Jeon   +2 more
exaly   +2 more sources

Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

IEEE Transactions on Electron Devices, 2006
Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations.
V D Kunz, T Uchino, C H De Groot
exaly   +1 more source

Simulation of amplified gate-induced-drain-leakage (GIDL) in short-channel SOI MOSFETs

Proceedings of International Workshop on Numerical Modeling of processes and Devices for Integrated Circuits: NUPAD V, 2002
Amplification of gate-induced-drain-leakage current has been reported for short channel MOS-transistors on SOI substrate. Here, we show that this effect is reproduced consistently by 2D-device simulation when a band-to-band tunneling model is included.
A. von Schwerin, W. Bergner, K. Jacobs
openaire   +2 more sources

A capacitor-less 1T-DRAM cell with vertical surrounding gates using gate-induced drain-leakage (GIDL) current

2008 IEEE Silicon Nanoelectronics Workshop, 2008
A capacitor-less one-transistor DRAM cell with surrounding gate MOSFET with vertical channel (SGVC) using gate-induced drain leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact ionization current, the write operation with GIDL current provides high sensing margin owing to higher ...
Han Ki Chung, Hoon Jeong, Yeun Seung Lee, Jae Young Song, Jong Pil Kim, Sang Wan Kim, Jae Hyun Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park   +9 more
openaire   +1 more source

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005
We demonstrate that for aggressively scaled FinFETs, with 2nm HfO 2 and TiN metal gate (i.e., workfunction close to midgap), several parasitic leakage mechanisms that impact the off-state current become dominant. We provide a detailed characterization of these mechanisms as well as design guidelines for eliminating them by careful junction dopant ...
T. Hoffmann, A. Dixit, K. De Meyer, M. Jurczak, S. Biesemans, G. Doornbos, I. Ferain, N. Collaert, P. Zimmerman, M. Goodwin, R. Rooyackers, A. Kottantharayil, Y. Yim   +12 more
openaire   +1 more source

Design of SOI FinFET on 32nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Solid-State Electronics, 2009
Recently, minimizing the standby power is considered as a critical issue in high-density, mobile CMOS technology. One of the major sources of the leakage current in off-state of ultra-small MOSFET is gate-induced drain leakage (GIDL) which is mainly composed of inter-band and trap-assisted tunneling.
null Seongjae Cho, null Jung Hoon Lee, S. O'uchi, K. Endo, M. Masahara, null Byung-Gook Park   +5 more
openaire   +1 more source

Novel design to improve band to band tunneling and gate induced drain leakages (GIDL) in cylindrical gate all around (GAA) MOSFET

Microsystem Technologies, 2017
In this paper a cylindrical Dual Metal (DM) Dielectric Engineered (DE) Gate All Around (GAA) MOSFET has been proposed to resolve a big issue of Gate Inducted Drain leakage (GIDL) current in cylindrical Gate All Around (GAA) MOSFET to enhance the device reliability. Dual Metal Dielectric Engineered Gate All Around (DMDEGAA) MOSFET has been compared with
Sonam Rewari, Vandana Nath, Subhasis Haldar, S. S. Deswal, R. S. Gupta   +4 more
openaire   +1 more source