Results 121 to 130 of about 3,848,813 (157)
IEEE Electron Device Letters, 2009 A soft-programming-free operation method in unified RAM (URAM) is presented. An oxide/nitride/oxide (O/N/O) layer and a floating-body are integrated in a FinFET, thereby providing the versatile functions of a high-speed capacitorless 1T-DRAM, as well as nonvolatile memory, and the mode of the memory cell can be selected and independently utilized ...
Yang-Kyu Choi +2 more
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Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs
Current Applied Physics, 2020Abstract The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET.
Changhwan Shin, Gihun Choe
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IEEE Transactions on Electron Devices, 2009
In this paper, we successfully demonstrated gate-induced drain leakage (GIDL) improvements by millisecond flash anneal (MFLA) on a DRAM product. Fundamental studies on blanket wafers and the device characteristics of product wafers showed positive results. These proved that MLFA has good potential for DRAM application.
Chao-Sung Lai
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In this paper, we successfully demonstrated gate-induced drain leakage (GIDL) improvements by millisecond flash anneal (MFLA) on a DRAM product. Fundamental studies on blanket wafers and the device characteristics of product wafers showed positive results. These proved that MLFA has good potential for DRAM application.
Chao-Sung Lai
exaly +2 more sources
Indian Journal of Physics, 2020
In this paper, an analytical paradigm for the gate-induced drain leakage (GIDL) for shallow extension engineered dual metal surrounding gate (SEE-DM-SG) MOSFET using superposition technique with appropriate boundary conditions is proposed. Electric field, Ez, gate-induced drain leakage current, IGIDL, and surface potential have been modeled.
Sonam Rewari, Anubha Goel, R S Gupta
exaly +2 more sources
In this paper, an analytical paradigm for the gate-induced drain leakage (GIDL) for shallow extension engineered dual metal surrounding gate (SEE-DM-SG) MOSFET using superposition technique with appropriate boundary conditions is proposed. Electric field, Ez, gate-induced drain leakage current, IGIDL, and surface potential have been modeled.
Sonam Rewari, Anubha Goel, R S Gupta
exaly +2 more sources
IEEE Transactions on Electron Devices, 2006
A capacitorless one-transistor (1T)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude ...
Tetsu Tanaka
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A capacitorless one-transistor (1T)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude ...
Tetsu Tanaka
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2009 IEEE International Memory Workshop, 2009
A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time.
Thomas Skotnicki +2 more
exaly +3 more sources
A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time.
Thomas Skotnicki +2 more
exaly +3 more sources
Gate-Induced-Drain-Leakage (GIDL) in CMOS Enhanced by Mechanical Stress
IEEE Transactions on Electron Devices, 2022Anastasiia Kruv +2 more
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2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 2022
Sonam Rewari
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Sonam Rewari
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IEEE Transactions on Electron Devices, 2006 Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations.
Takashi Uchino, P Ashburn
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