Results 71 to 80 of about 2,685 (171)
Low-power spatial computing using dynamic threshold devices [PDF]
, 2005 Asynchronous spatial computing systems exhibit only localized communication, their overall data-flow being controlled by handshaking. It is therefore straightforward to determine when a particular part of such a system is active.
Beckett, P
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GIDL 스트레스 조건 하에서 나노 크기 PMOSFET 열화 분석 [PDF]
, 2017 학위논문 (석사)-- 서울대학교 대학원 공과대학 전기·정보공학부, 2017. 8. 이종호.The device degradation under gate-induced drain leakage (GIDL) mode stress is studied in nano-scale p-MOSFET for DRAM peripheral circuit.
조수앙
core
Analysis of Random Telegraph Noise after Soft Breakdown in the Gate Induced Drain Leakage Current [PDF]
, 2013 학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 신형철.A Random Telegraph Noise (RTN) in leakage current has been important for discovering the cause of Variable Retention Time (VRT) in Dynamic Random Access Memory (DRAM) cell transistor.
이슬기
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The Effect of Gate-Induced Drain Leakage (GIDL) on Scaled MOSFETS of Low Power Consumptions [PDF]
, 2017 This project is aimed to study the impact of GateInduced Drain Leakage (GIDL) on scaled Metal-OxideSemiconductor Field-Effect Transistor (MOSFET) for low power efficient application. The MOSFET is operated with low power consumption. Microchip industries
Bolqiah Edrisa, Muhammad Zuhair +4 more
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Design of a reliability methodology: Modelling the influence of temperature on gate Oxide reliability [PDF]
, 2007 An Integrated Reliability Methodology (IRM) is presented that encompasses the changes that technology growth has brought with it and includes several new device degradation models.
Owens, Gethin Lloyd
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ESD characterization of planar InGaAs devices [PDF]
We present a comprehensive study of ESD reliability (TLP) on planar nMOSFETs with In0.53Ga0.47As as the channel material. Two types of traps are found during ESD stress.
Alian, A +15 more
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Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA [PDF]
, 2017 IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications.
Río Jiménez, Jaume del
core +1 more source
3나노 노드 소자에서 기들 측면의 스페이서 최적화 [PDF]
, 2019 학위논문(석사)--서울대학교 대학원 :공과대학 전기·정보공학부,2019. 8. 신형철.본 논문에서는 오프 상태 누설 전류의 관점에서 게이트 측벽 스페이서의 구조 및 물질 최적화를 3nm 노드 나노 플레이트 소자에서 수행했다. 첫째, 게이트 누설 전류의 주 요인 인 기들 (GIDL) 전류와 능동 성능 (온 전류, 온 / 오프 전류 비)가 게이트 측벽 스페이서와 게이트 및 소스.드레인과의 구조적 상관 관계에 따라 공동 최적화되었다.
류동현
core
Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature [PDF]
, 2009 A study on the influence of phosphorus implanted source/drain features on the off-state performance of transistors fabricated in thin-film crystalline silicon at low temperature is presented.
Singh, Siddhartha
core +1 more source
, 2023 In this paper, we have characterized an AlGaN/GaN High Electron Mobility Transistor (HEMT) with a short gate length (Lg $\approx$ 0.15$\mu$m). We have studied the effect of short gate length on the small signal parameters, linearity parameters and gm-gd ...
Ghosh, Santanu +5 more
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