Results 131 to 140 of about 1,624 (169)

PMOSFET anti-fuse using GIDL-induced-HEIP mechanism

Microelectronics Reliability, 2010
Abstract We propose a novel electrical fuse (e-fuse) program procedure using shallow trench isolation (STI) edge trapping mechanism of PMOSFET by applying AC pulses. We obtained flash characteristics using conventional PMOSFET structure, when injected AC pulse on source node under off-state condition (Vg = high, Vd = low).
J.Y. Seo, J.E. Seok, W.S. Kim, N.H. Cha, J.S. Kang, B.S. So   +5 more
openaire   +1 more source

HCD-Induced GIDL Increase and Circuit Implications

2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019
In this paper we review the physics of gate-induced drain leakage (GIDL) increase due to hot carrier degradation (HCD) and the proposed modelling for reliability simulations. A case study of an analog circuit where this phenomenon leads to an overall increase of static power consumption over time is shown.
Edoardo Ceccarelli, Kevin Manning, Giuseppe Macera, Dennis Dempsey, Colm Heffernan   +4 more
openaire   +1 more source

Effects of X-ray irradiation on GIDL in MOSFETs

IEEE Electron Device Letters, 1992
The effect of X-ray irradiation on the gate-induced drain leakage (GIDL) is shown to be mostly due to the electrostatic effect of the trapped positive charge in n-channel MOSFETs. In p-channel MOSFETs, in addition, irradiation increases the interface-state-assisted tunneling component of the GIDL.
A. Acovic, C.C.-H. Hsu, L.-C. Hsia, A. Balasinski, T.-P. Ma   +4 more
openaire   +1 more source

Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs

IEEE Electron Device Letters, 2009
In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the off state. However, our experimental results reveal that the capacitance
null Chia-Sheng Lin, null Ying-Chung Chen, null Ting-Chang Chang, null Shih-Ching Chen, null Fu-Yen Jian, null Hung-Wei Li, null Te-Chih Chen, null Chi-Feng Weng, null Jin Lu, null Wei-Che Hsu   +9 more
openaire   +1 more source

GIDL current degradation in LDD nMOSFET under hot hole stress

Journal of Semiconductors, 2011
The degradation of gate-induced drain leakage (GIDL) current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter IDIFF.IDIFF is the difference of GIDL currents measured under two conditions of drain voltage VD = 1.4 V and gate voltage VG = −1.4 V while VDG is fixed. After the stress GIDL currents decay due to holes trapping
Haifeng Chen, Xiaohua Ma, Lixin Guo, Huimin Du   +3 more
openaire   +2 more sources

GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications

IEEE Electron Device Letters, 2013
Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped- and undoped-channel FinFET devices through 3-D process and device simulations is presented. For a given gate length (LG) and gate dielectric thickness, the placement and grading of the drain junction and the channel doping are shown to have a tremendous impact on GIDL ...
Pranita Kerber, Qintao Zhang, Siyuranga Koswatta, Andres Bryant   +3 more
openaire   +1 more source

Impact of substrate bias on GIDL for thin-BOX ETSOI devices

2011 International Conference on Simulation of Semiconductor Processes and Devices, 2011
We present a detailed analysis of substrate bias (V bb ) impact on gate induced drain leakage (GIDL) for thin-BOX extremely thin silicon-on-insulator (ETSOI) with BOX thickness (T BOX ) ranging from 10 to 50 nm and inversion layer thicknesses (T INV ) ranging from 1.1 to 1.3 nm.
P. Kulkarni, Q. Liu, A. Khakifirooz, Y. Zhang, K. Cheng, F. Monsieur, P. Oldiges   +6 more
openaire   +1 more source

GIDL effect observed in FinFET shapes and Vt implant energy

2018 7th International Symposium on Next Generation Electronics (ISNE), 2018
The leakage of FinFETs with the different features and V t implant energy is observed and strongly related to the previous factors. Due to the process controllability, especially in photo-lithography, the multi-channel shape to promote the drive current seems not easy to be controlled well and deteriorates the desired target.
Ting-Wei Chao, Tien-Szu Shen, Chii-Ruey Lin, Ching-Chuan Chou, Chia-Hsien Chang, Wen-Shiang Liao, Mu-Chun Wang   +6 more
openaire   +1 more source

Analysis of GIDL Dependence on STI-induced Mechanical Stress

2005 IEEE Conference on Electron Devices and Solid-State Circuits, 2006
The mechanical stress induced by shallow trench isolation (STI) signifilcantly affects the device behavior in the advanced CMOS technology. This paper presents an STI-dependent gate-induced drain leakage (GIDL) model and investigates the physical mechanisms in this phenomenon.
openaire   +1 more source

Practical finFET design considering GIDL for LSTP (low standby power) devices

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2006
Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive
K. Tanaka, K. Takeuchi, M. Hane
openaire   +1 more source