Results 11 to 20 of about 1,624 (169)

Interface-state-induced degradation of GIDL current in n-MOSFETsunder hot-carrier stress [PDF]

Proceedings 1996 IEEE Hong Kong Electron Devices Meeting, 1996
The dependence of increase in post-stress gate-induced-drain-leakage (GIDL) current in n-MOSFET's on creation of interface states (ΔDit) during hot-carrier stress with VG = 0.5 VD was investigated.
Lai, PT, Liu, BY, Xu, JP, Zeng, X
core   +4 more sources

Unveiling the Hybrid‐Channel (poly‐Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL‐Assisted Erase Operation

Small Structures
Oxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field‐effect mobility and superior large‐area uniformity but suffering from low thermal stability, trade‐off between mobility and stability, and the
Su‐Hwan Choi, Jae‐Min Sim, Jeongmin Shin, Seong‐Hwan Ryu, Taewon Hwang, So Young Lim, Hye‐Jin Oh, Jae‐Hyeok Kwag, Jun‐Yeoub Lee, Ki‐Cheol Song, Yeonhee Lee, Minju Song, Junghwan Kim, Chang‐Kyun Park, Yun‐Heub Song, Jin‐Seong Park   +15 more
doaj   +2 more sources

Self-Curable Synaptic Ferroelectric FET Arrays for Neuromorphic Convolutional Neural Network. [PDF]

Adv Sci (Weinh), 2023
The primary challenge that ferroelectric field‐effect transistors face is their vulnerability to the repeated program/erase cycle. To solve this issue, an efficient self‐curing method is presented. The proposed method successfully recovers synaptic fatigue damage, enhancing learning accuracy in the convolutional neural network.
Shin W, Im J, Koo RH, Kim J, Kwon KR, Kwon D, Kim JJ, Lee JH, Kwon D.   +8 more
europepmc   +2 more sources

Stacked Nanosheet Gate-All-Around Morphotropic Phase Boundary Field-Effect Transistors. [PDF]

Adv Sci (Weinh)
This study proposes a material design using ferroelectric‐antiferroelectric mixed‐phase HZO to achieve steep subthreshold swing and non‐hysteretic on‐current enhancement in morphotropic phase boundary field‐effect transistors (MPB‐FETs). For the first time, two‐stacked nanosheet GAA MPB‐FETs with optimized HZO are demonstrated, validating superior ...
Kim S, Kim HM, Kwon KR, Kwon D.
europepmc   +2 more sources

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE Journal of the Electron Devices Society, 2023
In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase
Michelly De Souza, Antonio Cerdeira, Magali Estrada, Sylvain Barraud, Mikael Casse, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello   +7 more
doaj   +1 more source

Simulation Acceleration of Bit Error Rate Prediction and Yield Optimization of 3D V-NAND Flash Memory

IEEE Access, 2023
When designing 3D V-NAND technologies with a gate induced drain leakage (GIDL) assisted erase scheme, many experiments must be conducted to determine the optimal GIDL design targets to achieve fast erase performance and secure yield characteristics ...
Yohan Kim, Soyoung Kim
doaj   +1 more source

Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model

IEEE Journal of the Electron Devices Society, 2022
We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL)
Fei Mo, Jiawen Xiang, Xiaoran Mei, Yoshiki Sawabe, Takuya Saraya, Toshiro Hiramoto, Chun-Jung Su, Vita Pi-Ho Hu, Masaharu Kobayashi   +8 more
doaj   +1 more source

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Memories - Materials, Devices, Circuits and Systems, 2023
TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust ...
Koji Sakui, Yisuo Li, Masakazu Kakumu, Kenichi Kanazawa, Iwao Kunishima, Yoshihisa Iwata, Nozomu Harada   +6 more
doaj   +1 more source

Advancing the Frontiers of HfO₂-Based Ferroelectric Memories: Innovative Concepts from Materials to Applications. [PDF]

Adv Mater
HfO2‐based ferroelectric materials are promising for next‐generation memory technologies by providing outstanding performance aligning with data‐centric computing needs. This review details recent advancements in materials, devices, and integration for HfO2‐based memories, with the goal of identifying both the technological opportunities and remaining ...
Zhou Z, Li L, Feng Y, Wang X, Zheng Z, Jiao L, Zheng H, Shi Y, Ang KW, Gong X.   +9 more
europepmc   +2 more sources

Using electrical impedance tomography to characterize lung impairment of children with primary ciliary dyskinesia: A pilot cross‐sectional study

Pediatric Pulmonology, Volume 58, Issue 4, Page 1051-1058, April 2023., 2023
Abstract Background In children with primary ciliary dyskinesia (PCD), measures more sensitive than spirometry are needed to characterize underlying pulmonary impairment. Electrical impedance tomography (EIT) is a promising noninvasive method for monitoring the distribution of lung ventilation, and it does not require patient collaboration. We aimed to
Mariacarola Pensabene, Simone Gambazza, Federica Carta, Alessia Rocchi, Mara Lelii, Barbara Madini, Vittoria Hassan, Marta Piotto, Maria Francesca Patria   +8 more
wiley   +1 more source