Results 21 to 30 of about 1,624 (169)
Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors
IEEE Journal of the Electron Devices Society, 2022 A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed.
Jie Gu +11 more
doaj +1 more source
Advanced Electronic Materials, Volume 9, Issue 1, January 2023., 2023 Three‐gate reconfigurable transistors based on Al‐Si‐Al heterostructures with single‐elementary Al contacts, capable of dynamically altering between n‐ or p‐type operations even during run‐time are proposed. Exploiting reconfigurability on transistor level and showing comparability with complementary metal‐oxide‐semiconductor technology, a ...
Raphael Böckle +8 more
wiley +1 more source
Emerging reconfigurable electronic devices based on two‐dimensional materials: A review
InfoMat, Volume 4, Issue 10, October 2022., 2022 An intense survey of novel reconfigurable devices based on 2D materials is presented with a focus on reconfigurable transistors that offer run‐time control of charge carriers, threshold voltage, and subthreshold swing, and reconfigurable heterostructures manifested as multiple device configurations in one device. The working principles of these devices
Wenwen Fei +4 more
wiley +1 more source
Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET
Modelling and Simulation in Engineering, Volume 2022, Issue 1, 2022., 2022 Ferroelectric negative capacitance materials have now been proposed for lowering electronics energy dissipation beyond basic limitations. In this paper, we presented the analysis on the performance of negative capacitance (NC) FinFET in comparison with conventional gate dielectrics by using a separation of variables approach, which is an optimal quasi ...
Sayem Ul Alam +6 more
wiley +1 more source
Generic radiation hardened photodiode layouts for deep submicron CMOS image sensor processes [PDF]
, 2011 Selected radiation hardened photodiode layouts, manufactured in a deep submicron CMOS Image Sensor technology, are irradiated by 60Co gamma-rays up to 2.2 Mrad(SiO2) and studied in order to identify the most efficient structures and the guidelines ...
Cervantes, Paola +5 more
core +1 more source
Review of ferroelectric field‐effect transistors for three‐dimensional storage applications
Nano Select, Volume 2, Issue 6, Page 1187-1207, June 2021., 2021 The ideal hysteresis of the ferroelectric thin film for ferroelectric field effect transistor‐based 3‐dimensional storage devices. The navy‐colored solid curve represents the typical displacement field (Dfer) versus voltage (Vfer) hysteresis. The two vertical arrows indicate that only a small portion of the remanent polarization (Pr) is required for ...
Hyeon Woo Park +2 more
wiley +1 more source
Applied Sciences, 2018 Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage.
Hsin-Hui Hu, Yan-Wei Zeng, Kun-Ming Chen
doaj +1 more source
Simulation of Graphene Nanoribbon Field Effect Transistors [PDF]
, 2007 We present an atomistic three-dimensional simulation of graphene nanoribbon field effect transistors (GNR-FETs), based on the self-consistent solution of the 3D Poisson and Schroedinger equation with open boundary conditions within the non-equilibrium ...
Fiori, G., Iannaccone, G.
core +1 more source
Thermal synergies in 50 nanometer CMOS and below
IET Circuits, Devices &Systems, Volume 15, Issue 2, Page 183-196, March 2021., 2021 Abstract An analysis of the metal oxide semiconductor field effect transistor (MOSFET) in strong inversion indicates two bias regions, in each of its triode and saturation conditions, whose distinct properties are elaborated and shown to lead to simple, systematic, design procedures for achieving low temperature coefficient (TC) voltages (<±100 ppm/°C)
F.S. Shoucair
wiley +1 more source
Correlation between hot-carrier-induced interface states and GIDL current increase in N-MOSFET's [PDF]
, 1998 Correlation between created interface states and GIDL current increase in n-MOSFET's during hot-carrier stress is quantitatively discussed. A trap-assisted two-step tunneling model is used to relate the increased interface-state density (ADH) with the ...
Cheng, YC +4 more
core +1 more source