Results 51 to 60 of about 1,624 (169)
Charge trapping properties of N2O-treated NH3-nitrided oxides under high-field stress [PDF]
Conference Theme: Asia-Pacific Microelectronics 2000A new technique, namely N2O treatment of NH3-nitrided oxides (NON20), is proposed to fabricate thin oxide.
Lai, PT, Ng, WT, Zeng, X
core +1 more source
1 Transistor‐Dynamic Random Access Memory as Synaptic Element for Online Learning
This work demonstrates the feasibility of utilizing capacitor‐less 1 transistor(1 T)‐dynamic random access memory as synaptic element with multilevel capability, large dynamic range of conductance, high linearity, ultralow energy consumption, high endurance exceeding 1015 cycles, and large integration density for artificial‐intelligence‐of‐things edge ...
MD Yasir Bashir +2 more
wiley +1 more source
Modeling, Simulation, and Analysis of Novel Threshold Voltage Definition for Nano‐MOSFET
Threshold voltage (VTH) is the indispensable vital parameter in MOSFET designing, modeling, and operation. Diverse expounds and extraction methods exist to model the on‐off transition characteristics of the device. The governing gauge for efficient threshold voltage definition and extraction method can be itemized as clarity, simplicity, precision, and
Yashu Swami +2 more
wiley +1 more source
Statistical leakage estimation in 32nm CMOS considering cells correlations [PDF]
International audienceIn this paper a method to estimate the leakage power consumption of CMOS digital circuits taking into account input states and process variations is proposed.
Beigné, Edith +4 more
core +5 more sources
Enhancing Device Performance with High Electron Mobility GeSn Materials
Vertical gate‐all‐around nanowire n‐FETs based on GeSn‐alloys with Sn‐contents of 8% and 11% are presented. A great improvement in Ion, gm, and SS is found with increased Sn‐content. A fivefold increase in on‐current is observed for 11%‐GeSn compared to Ge, underlining the potential of GeSn for nanoelectronics applications.
Yannik Junk +10 more
wiley +1 more source
Dual-Doped Cylindrical Bit-Line Pad for High-Efficiency Bulk Erase in V-NAND Flash
We propose a novel dual-doped cylindrical bit-line (DDC-BL) pad structure for vertical NAND (V-NAND) flash memory to enable efficient bulk erase operation through direct hole injection.
Choasub Kim +4 more
doaj +1 more source
The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display.
KwangHyun Choi +5 more
doaj +1 more source
Human response to vibration in residential environments [PDF]
This paper presents the main findings of a field survey conducted in the United Kingdom into the human response to vibration in residential environments.
Condie, J +6 more
core +2 more sources
An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution
This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance ...
Min Hee Cho +7 more
doaj +1 more source
Distinguishing capture cross-section parameter between GIDL erase compact model and TCAD
Abstract A compact model of 3D NAND enables simulation at circuit- or system-level. Although a compact model for gate-induced-drain-leakage (GIDL)-assisted erase was proposed in a previous study, it is difficult to use practically because it has not been properly validated.
Kul Lee, Hyungcheol Shin
openaire +1 more source

