Results 71 to 80 of about 1,624 (169)

Characteristics of degradation under GIDL stress in ultrathin gate oxide LDD nMOSFET’s

Acta Physica Sinica, 2007
The threshold voltage (VTH) degradation have been investigated under GIDL　(gate induced drain leakage) stresse in LDD nMOSFET with 1.4　nm-thick gate oxide. The trapped holes and interface states generated in the stress process at interface around LDD overlapping region result in the increase in VTH.
null Chen Hai-Feng, null Hao Yue, null Ma Xiao-Hua, null Tang Yu, null Meng Zhi-Qin, null Cao Yan-Rong, null Zhou Peng-Ju   +6 more
openaire   +1 more source

Investigation of the Scalability of Emerging Nanotube Junctionless FETs Using an Intrinsic Pocket

IEEE Journal of the Electron Devices Society, 2019
The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their
Aakash Kumar Jain, Jaspreet Singh, Mamidala Jagadesh Kumar   +2 more
doaj   +1 more source

Comprehensive Hammering and Parasitic BJT Effects in Vertically Stacked DRAM

IEEE Access
This study investigates the row hammer tolerance and potential degradation by capacitive crosstalk (CC) and parasitic bipolar junction transistor (BJT) effect in vertically stacked dynamic random-access memory (VS-DRAM) using technology computer-aided ...
Minki Suh, Minsang Ryu, Jonghyeon Ha, Minji Bang, Dabok Lee, Hojoon Lee, Hyunchul Sagong, Jungsik Kim   +7 more
doaj   +1 more source

Electrical Effect of Nitrogen Implanted Into LDD of MOSFETs

IEEE Journal of the Electron Devices Society
The motivation of this study was to solve the high $\rm I_{D,off}$ problem in 8 Volt N-channel MOSFET. We experimented with implanting nitrogen into LDD at various doses.
Yoo Seon Song, Markus Lenski, Mohammed F. Karim, Keith Flynn, Jan Hoentschel, Carsten Peters, Jens-Uwe Sachse, Omur Isil Aydin, Jun Wu, Bastian Hausdorfer, Mahesh Siddabathula, Konrad Semmler, Jurgen Daleiden   +12 more
doaj   +1 more source

GidL: A grounder for FO+

, 2008
sponsorship: Fonds voor Wetenschappelijk Onderzoek Vlaanderen (FWO-Vlaanderen)
Wittocx, Johan, Mariën, Maarten, Denecker, Marc   +2 more
openaire   +1 more source

Harbor porpoise displacement by a solitary bottlenose dolphin in the Baltic Sea

Marine Mammal Science, Volume 41, Issue 1, January 2025.
Olga A. Filatova, Ivan D. Fedutin, Freja Jakobsen, Lotte Kindt‐Larsen, Magnus Wahlberg   +4 more
wiley   +1 more source

Vertical Surrounding Gate Transistor for High Density and Low Voltage Operation in DRAM

IEEE Access
In this article, a honeycomb vertical surrounding gate access transistor array scheme is proposed to further decrease the DRAM cell area with aggressively shrink bit line (BL) pitch and word line (WL) pitch adopting the ZigZag BL and WL air gap.
Wenqi Wang, Sang Don Yi, Fu Li, Qingchen Cao, Jiangliu Shi, Bok-Moon Kang, Meichen Jin, Chang Liu, Zhenhua Wu, Guilei Wang, Chao Zhao   +10 more
doaj   +1 more source

Synergistic regional emission reductions in China: Network evolution, spatial and temporal characteristics, and driving factor

Ecological Indicators
Synergistic regional emission reduction (SRER) is an important part of the strategy to achieve carbon neutrality. In this paper, a system efficiency value-added model is proposed to measure the strength of SRER network relationships for 40,186 sets of ...
Bin Liao, Caihong Tian, Tian Zhou, Lei Han   +3 more
doaj   +1 more source

Device Characterization of 0.8-µm CMOS Technology [PDF]

, 2000
The development of the O.8-um CMOS technology was carried out in Mimos Berhad and is considered to be the first in-house development to be done in Malaysia.
Kooh, Roy Jinn Chye
core  

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory With Separated Source-Line

IEEE Access
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj   +1 more source