Results 141 to 150 of about 236 (173)

An accurate scalable model for 700V LDMOS

2016 China Semiconductor Technology International Conference (CSTIC), 2016
This paper discusses a highly scalable model of 700V LDMOS (Lateral Diffused MOS) device. The device model includes several key steps like self-heating characterization, parasitic resistance removing and dimension scalability. A SUBCKT approach is presented for accurate modeling of some special effects, such as quasi-saturation and gate/junction ...
Pingliang Li, Zhengnan Wang, Sunny Zhang
openaire   +1 more source

Compact model of LDMOS for circuit simulation

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006
A new compact LDMOS is introduced in this paper for circuit simulation. Features covered in this model relevant for a LDMOS device include: unique bias dependent drift region resistance model accounting for velocity saturation, bias dependent overlap region resistance model, dual Isub model to model Iii current in different region in the device and ...
Yutao Ma, Ping Chen, Hancheng Liang, James Ma, Min-chie Jeng, Zhihong Liu   +5 more
openaire   +1 more source

LDMOS Modeling

IEEE Microwave Magazine, 2013
Szhau Lai, Christian Fager, Dan Kuylenstierna, Iltcho Angelov   +3 more
openaire   +1 more source

Interdigitated LDMOS

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2013
null Jaejune Jang, null Kyu-Heon Cho, null Dongeun Jang, null Minhwan Kim, null Changjoon Yoon, null Junsung Park, null Hyunsil Oh, null Chiho Kim, null Hyoungsoo Ko, null Keunho Lee, null Sangbae Yi   +10 more
openaire   +1 more source

Review of the SiC LDMOS power device

Journal of Semiconductors
Abstract Silicon carbide (SiC), as a third-generation semiconductor material, possesses exceptional material properties that significantly enhance the performance of power devices. The SiC lateral double-diffused metal–oxide–semiconductor (LDMOS) power devices have undergone continuous optimization, resulting in an increase in breakdown ...
Ziwei Hu, Jiafei Yao, Ang Li, Qi Sun, Man Li, Kemeng Yang, Jun Zhang, Jing Chen, Maolin Zhang, Yufeng Guo   +9 more
openaire   +1 more source

A novel BIST technique for LDMOS drivers

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014
Bruce C. Kim, Saikat Mondal, Friedrich Taenzler, Kenneth Moushegian   +3 more
openaire   +1 more source

Capacitance Modelling of LDMOS Transistors

30th European Solid-State Device Research Conference, 2000
E.C. Griffith, S.C. Kelly, J.A. Power, D. Bain, S. Whiston, P. Elbert, M. O'Neill   +6 more
openaire   +1 more source

Summary of Integration Concepts for LDMOS Transistors

2014
The final chapter of this textbook summarizes the integration concepts presented in Chap. 5 through Chap. 9. Comparison of integration densities and figures-of-merit represent a first methodology to evaluate these concepts with respect to applications requiring high efficiency or performance. Another methodology for comparison of device technologies is
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A simulation-based evaluation of single-event burnout mechanisms and varied SEB hardening designs in power LDMOS transistors

Microelectronics Reliability, 2022
Yibo Lei
exaly  

An embedded β-Ga2O3 layer in a SOI-LDMOS to improve breakdown voltage

Journal of Computational Electronics, 2022
Ali A Orouji, Dariush Madadi, Orouji Ali A   +2 more
exaly