Results 61 to 70 of about 1,986,606 (160)
Investigation of Retention Noise for 3-D TLC NAND Flash Memory
IEEE Journal of the Electron Devices Society, 2019 In this paper, the retention noise [electron emission statistics (EES)] after program operation of 3-D triple-level program cell (TLC) NAND flash memory is investigated.
Kunliang Wang +3 more
doaj +1 more source
A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND Flash Memory
IEEE Journal of the Electron Devices Society, 2022 Experimental results indicate that the conventional program suspend scheme in 3D NAND flash memory chip can generate unexpected additional read fail bits and reduce the reliability of 3D NAND flash memory. These extra read fail bits are observed when the
Zhichao Du +11 more
doaj +1 more source
Advanced Electronic Materials, EarlyView.Composition‐dependent structural evolution in GeXSe1‐X selector‐only memory (SOM) is correlated with device switching behavior. Increasing Ge strengthens network rigidity, suppresses atomic motion, and stabilizes threshold switching, while narrowing the memory window. The revealed structure–property relationship provides a guideline for compositionally
Tien Anh Nguyen +9 more
wiley +1 more source
An efficient fault detection algorithm for NAND flash memory
, 2011 As flash memory gains its momentum in the storage market of embedded systems, existing fault detection algorithms face serious challenges due to the special characteristics of NAND flash memory and the rapid degradation of its reliability.
Tei-Wei Kuo +4 more
core +1 more source
NAD Memory: A Hybrid Memory Device Combined With NAND Flash Memory and DRAM
IEEE AccessAdvancements in semiconductor technology have significantly improved the performance of DRAM and NAND flash, establishing them as high-speed main memory and high-capacity storage, respectively.
Sojoong Kim +3 more
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Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory
IEEE Access, 2021 This paper proposes a decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes, aiming to improve the error rate performance for NAND flash memory. Several NB-LDPC decoding methods for NAND flash memory have been studied. Some approaches
Kyeong Bin Park, Ki-Seok Chung
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Exploiting Ferroelectric and Spintronic Dynamics for Neural Network Computation
Advanced Intelligent Systems, EarlyView.Ferroelectric and spintronic devices, relying on the control of polarization and magnetization, offer intrinsically fast, durable, energy‐efficient, and low‐latency building blocks for analog in‐memory computing. The hysteretic dynamics of an order parameter are leveraged to provide nonvolatile, multistate memory and nonlinear switching. Brain‐inspired
Dashiell Harrison +4 more
wiley +1 more source
IEEE AccessNAND flash memory has emerged as a compelling platform for intrinsic security primitives because of its widespread use, scalable architecture, and rich device-level variability.
Pyi Phyo Aung +2 more
doaj +1 more source
Vertical NAND Flash Memory‐Based Bayesian Neural Networks With Intrinsic Gaussian Weight Sampling
Advanced Intelligent Systems, EarlyView.Commercial vertical NAND flash memory supports Bayesian neural networks by using paired cells to produce bell‐shaped weight distributions. Read voltage controls their spread without additional memory cells or changes to the array structure. Simulations based on device measurements demonstrate improved uncertainty estimation and accuracy gains of up to ...
Sung‐Ho Park +8 more
wiley +1 more source
Dynamic Forest: An Efficient Index Structure for NAND Flash Memory
, 2009 In this paper, we present an efficient index structure for NAND flash memory, called the Dynamic Forest (D-Forest). Since write operations incur high overhead on NAND flash memory, D-Forest is designed to minimize write operations for index updates.
Yang, Chul-Woong +3 more
core +1 more source