Compression-Assisted Adaptive ECC and RAID Scattering for NAND Flash Storage Devices
NAND flash memory-based storage devices are vulnerable to errors induced by NAND flash memory cells. Error-correction codes (ECCs) are integrated into the flash memory controller to correct errors in flash memory. However, since ECCs show inherent limits
Seung-Ho Lim, Ki-Woong Park
doaj +1 more source
A Survey on Flash Translation Layer for NAND Flash Memory [PDF]
The requirement for storage performance and capacity are increasing rapidly. NAND flash-based SSDs have been proposed as a reliable and speedy and low power consumption storage device. An important part of each SSDs is its flash translation layers (FTL).
P.K. Singh, Kumkum Dubey, Shailesh Kumar
openaire +1 more source
Radiation-Induced Error Mitigation by Read-Retry Technique for MLC 3-D NAND Flash Memory
In this article, we have evaluated the Read-Retry (RR) functionality of the 3-D NAND chip of multilevel-cell (MLC) configuration after total ionization dose (TID) exposure.
P. Kumari +5 more
semanticscholar +1 more source
Physics‐Based Compact Modeling of Advanced 3D Nanoscale Vertical NAND Flash Memory
For advanced 3D NAND flash memory, a unified compact model for SPICE is proposed that spans from the intrinsic unit cell to the full string and captures the electrostatic coupling with adjacent inhibit strings. It can successfully predict read behavior, program/erase dynamics, and interactions between neighboring cells, reflecting array‐level behavior ...
Ilho Myeong, Seonho Shin, Ickhyun Song
wiley +1 more source
Flash-memories in Space Applications: Trends and Challenges [PDF]
Nowadays space applications are provided with a processing power absolutely overcoming the one available just a few years ago. Typical mission-critical space system applications include also the issue of solid-state recorder(s).
Caramia, M. +4 more
core
Hardware‐Based On‐Chip Learning Using a Ferroelectric AND‐Type Array With Random Synaptic Weights
This work demonstrates an energy‐efficient on‐chip learning system using an Metal‐Ferroelectric‐Insulator‐Semiconductor FeAND synaptic array. By employing a feedback alignment scheme with a separate backward array using fixed random weights, the system overcomes directional limitations of AND‐type arrays and achieves robust, low‐power learning suitable
Minsuk Song +8 more
wiley +1 more source
Review of ferroelectric field‐effect transistors for three‐dimensional storage applications
The ferroelectric field‐effect transistor (FeFET) is one of the leading contenders to succeed charge‐trap‐based flash memory (CTF) devices in the current vertically‐integrated NAND flash storage market.
Hyeon Woo Park +2 more
doaj +1 more source
Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages
Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated.
Dongwoo Lee, Changhwan Shin
doaj +1 more source
Exploiting Ferroelectric and Spintronic Dynamics for Neural Network Computation
Ferroelectric and spintronic devices, relying on the control of polarization and magnetization, offer intrinsically fast, durable, energy‐efficient, and low‐latency building blocks for analog in‐memory computing. The hysteretic dynamics of an order parameter are leveraged to provide nonvolatile, multistate memory and nonlinear switching. Brain‐inspired
Dashiell Harrison +4 more
wiley +1 more source
Flash-DNA: Identifying NAND Flash Memory Origins Using Intrinsic Array Properties
Counterfeit electronics entering the globalized supply chain are a growing problem impacting manufacturers and consumers alike. This article introduces Flash-DNA, a new technique for identifying the original chip manufacturer of NAND flash memory, which ...
S. Sakib, A. Milenković, B. Ray
semanticscholar +1 more source

