Results 21 to 30 of about 29,884 (210)
Nand gate architectures for memory decoder [PDF]
INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY, 2013 This paper presents some nand gate design styles which when used in decoder reduces energy consumption and delay. Basically conventional, nor style nand, source coupled nand is discussed. The three designs conventional, nor style nand, source coupled nand, ranges in area, speed and power.
Shivkaran Jain, Arun Kr. Chatterjee
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Thermodynamics of Computation for CMOS NAND Gate
Journal of the Physical Society of Japan, 2023 Understanding how much energy is needed and dissipated as heat for a given computational system and for a given program is a physically interesting and practically important problem. However, the thermodynamic costs of computational systems are only partially understood. In this paper, we focus on a specific logic gate, the CMOS NAND gate, operating in
Daigo Yoshino, Yasuhiro Tokura
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Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
IET Computers & Digital Techniques, 2021 The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law.
Marshal Raj +2 more
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FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design
Micromachines, 2021 In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, by using which the circuit of AND gate and OR gate composed of memristors is built. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate
Liu Yang +3 more
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Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory
IEEE Journal of the Electron Devices Society, 2020 As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics ...
Xinlei Jia +11 more
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Nanomaterials, 2022 As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the
Xinyue Yu +6 more
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3D NAND Flash Based on Planar Cells
Computers, 2017 In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a “punch-and-plug” process—with gate-all ...
Andrea Silvagni
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Advanced Science, 2023 To avoid the complexity of the circuit for in‐memory computing, simultaneous execution of multiple logic gates (OR, AND, NOR, and NAND) and memory behavior are demonstrated in a single device of oxygen plasma‐treated gallium selenide (GaSe) memtransistor.
Shania Rehman +13 more
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Nanomaterials, 2023 Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture.
Hongsheng Hu +8 more
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Electronics Letters, 1992 An optical two input NAND gate with a high on/off contrast ratio (
X. An +7 more
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