Results 31 to 40 of about 29,884 (210)
Evaluating the reliability of NAND multiplexing with PRISM [PDF]
, 2005 Probabilistic-model checking is a formal verification technique for analyzing the reliability and performance of systems exhibiting stochastic behavior.
Benítez, Isabel +4 more
core +4 more sources
Investigation of Poly Silicon Channel Variation in Vertical 3D NAND Flash Memory
IEEE Access, 2022 Since the most of three dimensional (3D) NAND devices’ channel is composed of polysilicon grain, the actual 3D NAND channel has a wave-shaped channel, not uniform shape.
Inyoung Lee +3 more
doaj +1 more source
Implementation of Full Adder Using Nand Gates
International Journal for Research in Applied Science and Engineering Technology, 2023 : In digital electronics, there are different types of logic circuits used to perform different kinds ofarithmetic operations. One of them is adder. Adder (or Binary Adder) is a combinational logic circuit that performs the addition of two or more binary numbers and gives an output sum.
K. Anusuya, Dr. S. Kavitha
openaire +1 more source
Advanced Electronic Materials, 2023 A dual‐gate anti‐ambipolar transistor (AAT) with a two‐dimensional ReS2 and WSe2 heterojunction is developed. The characteristic Λ‐shaped transfer curves yielded by the bottom‐gate voltage are effectively controlled by the top‐gate voltage.
Yoshitaka Shingaya +7 more
doaj +1 more source
A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory
Micromachines, 2023 With gate length (Lg) and gate spacing length (Ls) shrinkage, the cell-to-cell z-interference phenomenon is increasingly severe in 3D NAND charge-trap memory. It has become one of the key reliability concerns for 3D NAND cell scaling.
Jianquan Jia +3 more
doaj +1 more source
Implementation of Boolean Functions Using Tunnel Field-Effect Transistors
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2020 Tunnel field-effect transistors (TFETs) are being examined as a possible replacement of MOSFETs for digital applications. However, TFETs have small ON-state current and, typically, exhibit reduced speed compared with conventional MOSFETs.
S. Garg, Sneh Saurabh
doaj +1 more source
Molecular Realization of a Quantum NAND Tree
, 2018 The negative-AND (NAND) gate is universal for classical computation making it an important target for development. A seminal quantum computing algorithm by Farhi, Goldstone and Gutmann has demonstrated its realization by means of quantum scattering ...
Aspuru-Guzik, Alán +4 more
core +1 more source
Conceptual design of spin wave logic gates based on a Mach-Zehnder-type spin wave interferometer for universal logic functions [PDF]
, 2014 We present conceptual designs of an emerging class of logic gates, including NOT, NOR, and NAND, that use traveling spin waves (SWs) in the gigahertz range and that are based on a Mach-Zehnder-type SW (MZSW) interferometer.
Gilbert T. L. +4 more
core +1 more source
Memories - Materials, Devices, Circuits and Systems, 2023 In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics.
Ajay Kumar +7 more
doaj +1 more source
Single spin universal Boolean logic
, 2008 Recent advances in manipulating single electron spins in quantum dots have brought us close to the realization of classical logic gates based on representing binary bits in spin polarizations of single electrons.
Amasha S +10 more
core +1 more source