Results 21 to 30 of about 2,221 (294)
Limits of Breach-Resistant and Snapshot-Oblivious RAMs
, 2023 Oblivious RAMs (ORAMs) are an important cryptographic primitive that enable outsourcing data to a potentially untrusted server while hiding patterns of access to the data. ORAMs provide strong guarantees even in the face of a persistent adversary that views the transcripts of all operations and resulting memory contents.
Persiano, Giuseppe, Yeo, Kevin
openaire +2 more sources
Resistive-Memory Embedded Unified RAM (R-URAM) [PDF]
, 2009 A disturb-free unified RAM (URAM) is demonstrated. It consists of a nonvolatile memory (NVM) and a capacitorless dynamic random access memory (DRAM) in a single-cell transistor. The NVM function is achieved by the resistive switching of an Al(2)O(3) film,
Kim, Sung-Ho +2 more
core +1 more source
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories [PDF]
, 2007 In this paper we study Complex Read Faults in SRAMs, a combination of various malfunctions that affect the read operation in nanoscale memories. All the memory elements involved in the read operation are studied, underlining the causes of the realistic ...
Luigi Dilillo +5 more
core +1 more source
Molecular dynamics simulation of amorphous HfO2 for resistive RAM applications [PDF]
, 2014 HfO2 is widely investigated as the favoured material for resistive RAM device implementation. The structural features of HfO2 play a fundamental role in the switching mechanisms governing resistive RAM operations, and a comprehensive understanding of the
BROGLIA, GIULIA +3 more
core +1 more source
Intrinsically Secure Non-Volatile Memory Using ReRAM Devices
IEEE Access, 2022 The paper describes a device-level encryption approach for implementing intrinsically secure non-volatile memory (NVM) using resistive RAM (ReRAM). Data are encoded in the ReRAM filament morphology, making it robust to both electrical and optical probing
Junjun Huan +5 more
doaj +1 more source
Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells [PDF]
, 2008 The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors.
Stefano Di Carlo +7 more
core +1 more source
Automating defects simulation and fault modeling for SRAMs [PDF]
, 2008 The continues improvement in manufacturing process density for very deep sub micron technologies constantly leads to new classes of defects in memory devices. Exploring the effect of fabrication defects in future technologies, and identifying new classes
Stefano Di Carlo +9 more
core +1 more source
DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability
Journal of Low Power Electronics and Applications, 2017 To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored.
Sparsh Mittal +2 more
doaj +1 more source
Ferroelectric tunnel junctions: current status and future prospect as a universal memory
Frontiers in Materials, 2023 The semiconductor industry is actively looking for an all-encompassing memory solution that incorporates the advantageous aspects of current technology. This features non-volatility, like that of Flash memory, high scalability, like that of both Dynamic ...
Urvashi Sharma +6 more
doaj +1 more source
An Improved BCH Code for Crossbar-Based Resistive RAM [PDF]
, 2016 Recently, the Error Correction Code(ECC) circuit has been applied to Resistive RAM(RRAM) that suffers from the process variations to improve the reliability and write power consumption.
Shengming Zhou +9 more
core +1 more source