Results 131 to 140 of about 5,289 (241)

High-density via RRAM cell with multi-level setting by current compliance circuits

Discover Nano
In this work, multi-level storage in the via RRAM has been first time reported and demonstrated with the standard FinFET CMOS logic process. Multi-level states in via RRAM are achieved by controlling the current compliance during set operations.
Yu-Cheng Hsieh, Yu-Cheng Lin, Yao-Hung Huang, Yu-Der Chih, Jonathan Chang, Chrong-Jung Lin, Ya-Chin King   +6 more
doaj   +1 more source

Resistance-dependent switching in NiO-based filamentary RRAM devices [PDF]

, 2010
Resistive switching memory (RRAM) attracts a growing research interest as potential high-density Flash replacement. Although several transition metal oxides have shown resistance switching capabilities, NiO is considered one of the most promising ...
IELMINI, DANIELE, LACAITA, ANDREA LEONARDO, NARDI, FEDERICO, CAGLI, CARLO   +3 more
core  

Accurate Power Analysis for Near-Vt RRAM-based FPGA [PDF]

, 2016
FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances.
Xifan Tang, De Micheli, Giovanni, Giovanni De Micheli, Pierre-emmanuel Gaillardon, Tang, Xifan, Gaillardon, Pierre-Emmanuel   +5 more
core  

Investigation of resistive random-accesss memory (RRAM) materials and devices [PDF]

, 2019
An advancement in the current technology is pushing for better technological memory devices in terms of performance and reliability. As the current technology such as DRAM and FLASH memory is reaching its limits in its technology to scale down, other ...
Sim, Wei Kiat
core  

Advances of embedded resistive random access memory in industrial manufacturing and its potential applications

International Journal of Extreme Manufacturing
Embedded memory, which heavily relies on the manufacturing process, has been widely adopted in various industrial applications. As the field of embedded memory continues to evolve, innovative strategies are emerging to enhance performance.
Zijian Wang, Yixian Song, Guobin Zhang, Qi Luo, Kai Xu, Dawei Gao, Bin Yu, Desmond Loke, Shuai Zhong, Yishu Zhang   +9 more
doaj   +1 more source

System Level Exploration of RRAM for SRAM Replacement [PDF]

, 2013
Recently an effective usage of the chip area plays an essential role for System-on-Chip (SOC) designs. Nowadays on-chip memories take up more than 50%of the total die-area and are responsible for more than 40% of the total energy consumption.
Dogan, Rabia
core  

A Rapid-prototyping CMOS-RRAM Integration Strategy. [PDF]

Microsyst Nanoeng
Tsiamis A, Stathopoulos S, Prodromakis T.   +2 more
europepmc   +1 more source

Event-Driven Neuromorphic Gaze Decoding via e-Skin Electrooculography. [PDF]

ACS Nano
Jeong S, Ko HW, Kang JH, Ko J, Sim I, Xu Z, Jeong H, Kim SI, Choi Y, Jo S, Shim JW, Seo PH, Chae MS, Kim Y, Rehman A, Yeon H, Park BI, Suh YW, Lee H, Kim J, Lee K, Bae SH, Park MC, Mun S.   +23 more
europepmc   +1 more source

A generic compact model for resistive memories and switches. [PDF]

Sci Rep
Jung S, Kim H, Park J, Kim S, Kim MH.
europepmc   +1 more source

Optimizing TiO₂/HfO₂ Multilayer RRAM for Self-Rectifying Characteristics. [PDF]

Micromachines (Basel)
Nam CH, Baek MH.
europepmc   +1 more source