Results 11 to 20 of about 779,893 (262)
Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions
Aerospace, 2020 Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects.
Ygor Q. Aguiar +6 more
doaj +1 more source
Single-Event Effects in CMOS Image Sensors [PDF]
IEEE Transactions on Nuclear Science, 2013 In this paper, 3T active pixel sensors (APS) are exposed to heavy ions (N, Ar, Kr, Xe), and single-event effects (SEE) are studied. Devices were fully functional during exposure, no single-event latch-up (SEL) or single-event functional interrupt (SEFI) happened.
Lalucaa, Valerian +4 more
openaire +4 more sources
Simulation of Single-Event Transient Effect for GaN High-Electron-Mobility Transistor
Micromachines, 2023 A GaN high-electron-mobility transistor (HEMT) was simulated using the semiconductor simulation software Silvaco TCAD in this paper. By constructing a two-dimensional structure of GaN HEMT, combined with key models such as carrier mobility, the effects ...
Zhiheng Wang +11 more
doaj +1 more source
Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node
Applied Sciences, 2022 Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should
Christopher J. Elash +6 more
doaj +1 more source
Bootstrapped Driver and the Single-Event-Upset Effect [PDF]
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020 As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP)
Mohammed Al-Daloo +3 more
openaire +3 more sources
NAIRAS Model Run‐On‐Request Service at CCMC
Space Weather, 2023 The Nowcast of Aerospace Ionizing RAdiation System (NAIRAS) version 3 model is available to the community through the Community Coordinated Modeling Center run‐on‐request (RoR) service.
C. J. Mertens +8 more
doaj +1 more source
Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs
Instruments, 2019 The usage of SRAM-based Field Programmable Gate Arrays on High Energy Physics detectors is mostly limited by the sensitivity of these devices to radiation-induced upsets in their configuration.
Raffaele Giordano +3 more
doaj +1 more source
Hardness assurance levels and requirements for single event effects testing of integrated circuits
Безопасность информационных технологий, 2020 The paper presents an analysis of existing approaches to estimation of single event rate (SER) in integrated circuits under effects of charged particles of space radiation environment.
Alexander I. Chumakov +13 more
doaj +1 more source
Applied Sciences, 2022 The pulsed laser has gradually become the standard method of studying the single-event effects of micro-nano devices, and it is a powerful supplement to heavy ion experiments on single-event effects.
Heng An +6 more
doaj +1 more source
Proton and γ-ray Induced Radiation Effects on 1 Gbit LPDDR SDRAM Fabricated on Epitaxial Wafer for Space Applications [PDF]
Journal of Astronomy and Space Sciences, 2016 We present proton-induced single event effects (SEEs) and γ-ray-induced total ionizing dose (TID) data for 1 Gbit lowpower double data rate synchronous dynamic random access memory (LPDDR SDRAM) fabricated on a 5 μm epitaxial layer (54 nm complementary
Mi Young Park +5 more
doaj +1 more source