Results 101 to 110 of about 13,512 (161)

Spectrum and prognosis of CAR-T-related endocrine toxicity: glucose/calcium dysregulation, pituitary axis disorders, and overlap with CRS. [PDF]

Front Med (Lausanne)
Liang J, Hu F, Li J, Zhai Y, Guo X, Xu J, Ye X, He J.   +7 more
europepmc   +1 more source

Case Report: Oral glutamatergic augmentation for trauma-related disorders with fluoxetine-/bupropion-potentiated dextromethorphan ± piracetam: a four-patient case series. [PDF]

Front Psychiatry
Cheung N.
europepmc   +1 more source

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A single event upset tolerant latch design

Microelectronics Reliability, 2018
Abstract This paper presents a single-event-upset tolerant latch design based on a redundant structure featuring four storage nodes (i.e. Quatro). The reference structure manifests single node upset issues when either of the two internal nodes is hit and observes a positive transient afterwards.
Haibin Wang, Li Chen
exaly   +2 more sources

Single event upset mitigation for FDP2008

2011 9th IEEE International Conference on ASIC, 2011
Highly integrated contemporary SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. In this paper, Fudan Design Environment (FDE) Triple Module Redundancy (TMR) approach for design triplication has been devised to meet high-reliability ...
Meng Yang, Gengsheng Chen
openaire   +1 more source

Single event upset in avionics

IEEE Transactions on Nuclear Science, 1993
Data from military/experimental flights and laboratory testing indicate that typical non-radiation-hardened 64 K and 256 K static random access memories (SRAMs) can experience a significant soft upset rate at aircraft altitudes due to energetic neutrons created by cosmic ray interactions in the atmosphere.
A. Taber, E. Normand
openaire   +1 more source

Estimating the effect of single-event upsets on microprocessors

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014
Evaluating the impact of single-event upsets (SEUs) on complex VLSI circuits in general, and microprocessors in particular, requires an interdisciplinary approach, that includes soft error modeling, accelerated measurements, derating of the raw error rates, and specialized design tools.
Cristian Constantinescu, Srini Krishnamoorthy, Tuyen Nguyen   +2 more
openaire   +1 more source

Design Optimization for Robustness to Single Event Upsets

24th IEEE VLSI Test Symposium, 2006
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model is integrated with area and performance constraints into an optimization framework based on geometric programming for design space ...
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram   +2 more
openaire   +1 more source

Detecting Single Event Upsets in Embedded Software

2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC), 2018
The past decade has seen explosive growth in the use of small satellites. Within this domain, there has been a growing trend to place more responsibility on the flight software (versus hardware) and an increasing adoption of consumer-grade microprocessors to satisfy this desire for increased processing capability while still minimizing size, weight ...
Robert G. Pettit IV, Aedan D. Pettit
openaire   +1 more source

Single Event Upset Testing

1988
Abstract : This report presents the results of an experimental program to characterize single event upset phenomena in selected bipolar memory devices irradiated with relativistic heavy ions. The principle objective was to determine the multibit upset rate at normal and parallel beam incidence angles.
Paul R. Measel, Jerry L. Wert, Dennis L. Oberg, Tommy L. Criswell   +3 more
openaire   +1 more source