A novel and accelerated method for integrated alignment and variant calling from short and long reads. [PDF]
Hu J +5 more
europepmc +1 more source
Transcriptional and Alternative Splicing Regulation of Autophagy and Vesicle Transport Pathways in Large Yellow Croaker Cells During Megalocytivirus Infection. [PDF]
Zheng Z +5 more
europepmc +1 more source
Beyond Blast Injury: Occupational Hygiene, Safety, and Toxicology Considerations for Mixed-Metal and Energetic-Chemical Exposures to Explosive Ordnance Disposal Personnel. [PDF]
Fry BG, Johnstone K, Pizzino S.
europepmc +1 more source
Single-event upset and snapback in silicon-on-insulator devices and integrated circuits [PDF]
The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important.
P E Dodd, D S Walsh, J R Schwank
exaly +1 more source
Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset
Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-node upset. This paper presents a novel memory cell design as variant of the DICE cell (that is tolerant to only a single event with a single-node upset).
Marco Ottavi, Fabrizio Lombardi
exaly +2 more sources
Related searches:
Single-Event-Upset (SEU) Awareness in FPGA Routing
2007 44th ACM/IEEE Design Automation Conference, 2007The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with ...
Shahin Golshan, Elaheh Bozorgzadeh
openaire +1 more source
Single event upset at gigahertz frequencies
IEEE Transactions on Nuclear Science, 1994Single Event Upset (SEU) characteristics of a digital emitter coupled logic (ECL) device clocking at 0.5, 1, and 3.2 GHz and at temperatures of 5, 75, and 105/spl deg/ C are presented. The test technique is explained. Observations of two types of upsets, phase upsets at low Linear Energy Transfer (LETs) and amplitude upsets at high LETs are also ...
M. Shoga +5 more
openaire +1 more source
Single-event upset in the PowerPC750 microprocessor
IEEE Transactions on Nuclear Science, 2001Proton and heavy ion upset susceptibility has been measured individually for six types of storage elements in an advanced commercial processor, the PowerPC750, from two manufacturers: Motorola and IBM. Data on interfering program malfunctions was also collected. Compared to earlier PPC603e results, the upset susceptibility has decreased somewhat.
G.M. Swift +4 more
openaire +1 more source
Single Event Upset: Experimental
1997The discussion in this chapter centers around the major single event upset (SEU) simulation sources. Their importance lies in the fact that simulation methods are one of the few means by which microcircuit susceptibility to SEU can be measured. These sources and source types are few in number, principally because of the somewhat unusual properties of ...
George C. Messenger, Milton S. Ash
openaire +1 more source
Single event upset rates in space
IEEE Transactions on Nuclear Science, 1992SEUs (single event upsets) in the CRRES (Combined Release and Radiation Effects Satellite) MEP (Microelectronic Package Space Experiment) showed a dramatic increase during a solar flare, the influence of the flare varied widely among device types, and a GaAs RAM (random access memory) showed a different response to the proton belts than some 51 RAMs ...
A. Campbell, P. McDonald, K. Ray
openaire +1 more source

