Results 281 to 290 of about 315,481 (343)

Single event upset mitigation for FDP2008

2011 9th IEEE International Conference on ASIC, 2011
Highly integrated contemporary SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. In this paper, Fudan Design Environment (FDE) Triple Module Redundancy (TMR) approach for design triplication has been devised to meet high-reliability ...
Meng Yang, Gengsheng Chen
openaire   +1 more source

A single event upset tolerant latch design

Microelectronics Reliability, 2018
Abstract This paper presents a single-event-upset tolerant latch design based on a redundant structure featuring four storage nodes (i.e. Quatro). The reference structure manifests single node upset issues when either of the two internal nodes is hit and observes a positive transient afterwards.
Haibin Wang, , Li Chen
exaly   +2 more sources

Single event upset in avionics

IEEE Transactions on Nuclear Science, 1993
Data from military/experimental flights and laboratory testing indicate that typical non-radiation-hardened 64 K and 256 K static random access memories (SRAMs) can experience a significant soft upset rate at aircraft altitudes due to energetic neutrons created by cosmic ray interactions in the atmosphere.
A. Taber, E. Normand
openaire   +1 more source

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