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A single-event transient tolerant optical receiver

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Single Event Transients in Digital CMOS—A Review

IEEE Transactions on Nuclear Science, 2013
The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of ...
Lloyd Massengill, Véronique Ferlet-Cavrois, V Ferlet-Cavrois   +2 more
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Single-Event Transient in FinFETs and Nanosheet FETs

IEEE Electron Device Letters, 2018
A single-event transient (SET) due to alpha particle strike is studied in 11- and 6-nm-bulk FinFETs and 6-nm-bulk nanosheet FET using 3-D TCAD simulation. The nanosheet device shows superior immunity to alpha particles due to the strong gate controllability.
Jungsik Kim, Jeong-Soo Lee, Jin-Woo Han, M. Meyyappan   +3 more
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Single Event Transient tolerant Count Min Sketches

Microelectronics Reliability, 2022
Publicado
Zhu, Jinhua, Jin, Jie, Gao, Zhen, Reviriego Vasallo, Pedro   +3 more
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Single event transients in combinatorial circuits

Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05, 2005
The single event upset (SEU) mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time consuming and must be performed for each different circuit topology, incident particle and track. This work presents an accurate and computer efficient analytical model for the evaluation of
Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt   +3 more
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Efficient analysis of single event transients

Journal of Systems Architecture, 2004
The effects of charged particles striking VLSI circuits and producing single event transients (SETs) are becoming an issue for designers who exploit deep sub-micron technologies; efficient and accurate techniques for assessing their impact on VLSI designs are thus needed.
SONZA REORDA, Matteo, VIOLANTE, MASSIMO
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