NASA Electronic Parts and Packaging (NEPP) Field Programmable Gate Array (FPGA) Single Event Effects (SEE) Test Guideline Update [PDF]
The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing ...
Berg, Melanie D., LaBel, Kenneth A.
core +1 more source
NEPP Independent Single Event Upset Testing of the Microsemi RTG4: Preliminary Data [PDF]
We present an independent investigation of heavy-ion single event effect data for the Microsemi RTG4 field programmable gate array (FPGA)
Berg, Melanie +2 more
core +1 more source
Spartan Daily, March 26, 2019 [PDF]
Volume 152, Issue 26https://scholarworks.sjsu.edu/spartan_daily_2019/1025/thumbnail ...
San Jose State University, School of Journalism and Mass Communications
core +2 more sources
Single event upset studies on the APV6 front end readout chip [PDF]
Bisello, D +9 more
core +1 more source
Single Event Upset tests of commercial FPGA for space applications [PDF]
Mattsson, S
core +1 more source
Incorporating Probability Models of Complex Test Structures to Perform Technology Independent FPGA Single Event Upset Analysis [PDF]
We present SEU test and analysis of the Microsemi ProASIC3 FPGA. SEU Probability models are incorporated for device evaluation.
Berg, M. D. +5 more
core +1 more source
NASA Electronic Parts and Packaging Field Programmable Gate Array Single Event Effects Test Guideline Update [PDF]
The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing ...
Berg, Melanie D., LaBel, Kenneth A.
core +1 more source
Single event upset tests of an 80Mbit/s optical receiver [PDF]
6th Workshop on Electronics for LHC Experiments +7 more
core +1 more source
Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit [PDF]
The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology.
French, Matthew +4 more
core +1 more source
Single event upset studies on the APV25 front end readout chip [PDF]
Bisello, D +10 more
core +1 more source

