Results 151 to 160 of about 13,512 (161)

Single-event upset and snapback in silicon-on-insulator devices and integrated circuits

IEEE Transactions on Nuclear Science, 2000
P E Dodd, D S Walsh, J R Schwank
exaly  

Low‐cost single event double‐upset tolerant latch design

Electronics Letters, 2018
Jianwei Jiang, Weiran Kong
exaly  

Single Event Upset in SOS Integrated Circuits

IEEE Transactions on Nuclear Science, 1987
J Choma, W A Kolasinski
exaly  

Single event upset characterization of the Pentium(R) MMX and Pentium(R) II microprocessors using proton irradiation

IEEE Transactions on Nuclear Science, 1999
D M Hiemstra
exaly  

Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset

IEEE Transactions on Device and Materials Reliability, 2014
Marco Ottavi, Fabrizio Lombardi
exaly  

Modification of single event upset cross section of an SRAM at high frequencies

IEEE Transactions on Nuclear Science, 1996
S Büchner, A B Campbell
exaly  

Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

IEEE Transactions on Nuclear Science, 2013
N J Gaspard, Z J Diggins, K Lilja
exaly  

Impact of Heavy Ion Energy and Nuclear Interactions on Single-Event Upset and Latchup in Integrated Circuits

IEEE Transactions on Nuclear Science, 2007
James R Schwank, M R Shaneyfelt, J A Felix   +2 more
exaly  

Single Event Upset (SEU) of Semiconductor Devices - A Summary of JPL Test Data

IEEE Transactions on Nuclear Science, 1983
exaly  

Single Event Upset Testing with Relativistic Heavy Ions

IEEE Transactions on Nuclear Science, 1984
exaly