Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset [PDF]
MicromachinesPlanar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses
Hongwei Zhang +6 more
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A Novel Low-Power and Soft Error Recovery 10T SRAM Cell [PDF]
Micromachines, 2023 In SRAM cells, as the size of transistors and the distance between transistors decrease rapidly, the critical charge of the sensitive node decreases, making SRAM cells more susceptible to soft errors.
Changjun Liu, Hongxia Liu, Jianye Yang
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Soft-Error-Resilient Static Random Access Memory with Enhanced Write Ability for Radiation Environments [PDF]
MicromachinesAs semiconductor technologies advance, SRAM cells deployed in space systems face heightened sensitivity to radiation-induced soft errors. In conventional 6T SRAM, when high-energy particles strike sensitive nodes, single-event upsets (SEUs) may occur ...
Se-Yeon Park, Eun Gyo Jeong, Sung-Hun Jo
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Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism [PDF]
Frontiers in Computational Neuroscience, 2023 Soft error has increasingly become a critical concern for SRAM-based field programmable gate arrays (FPGAs), which could corrupt the configuration memory that stores configuration data describing the custom-designed circuit architecture. To mitigate this
Yu Xie +3 more
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Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell [PDF]
Micromachines, 2023 In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics, especially in VLSI. This study analyzes the effect of single-event upset (SEU) in an SRAM cell, which employs a
Naheem Olakunle Adesina
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SEU Hardened D Flip-Flop Design with Low Area Overhead [PDF]
Micromachines, 2023 D flip-flop (DFF) is the basic unit of sequential logic in digital circuits. However, because of an internal cross-coupled inverter pair, it can easily appear as a single event upset (SEU) when hit by high-energy particles, resulting in the error in the ...
Chenyu Yin +3 more
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A guideline for heavy ion radiation testing for Single Event Upset (SEU) [PDF]
, 1984 A guideline for heavy ion radiation testing for single event upset was prepared to assist new experimenters in preparing and directing tests. How to estimate parts vulnerability and select an irradiation facility is described.
D. K. Nichols +2 more
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A Lightweight Method for Detecting and Correcting Errors in Low-Frequency Measurements for In-Orbit Demonstrators [PDF]
SensorsIn the pursuit of enhancing the technological maturity of innovative magnetic sensing techniques, opportunities presented by in-orbit platforms (IOD/IOV experiments) provide a means to evaluate their in-flight capabilities.
María-Ángeles Cifredo-Chacón +2 more
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Enhancing the Reliability of AD936x-Based SDRs for Aerospace Applications via Active Register Scrubbing and Autonomous Fault Recovery [PDF]
SensorsSingle Event Upsets (SEUs) in Commercial Off-The-Shelf (COTS) Software-Defined Radios (SDRs) are frequent in a erospace applications, especially in GEO (Geostationary Orbit) orbit during severe solar activity, and can lead to unexpected register ...
Jinyang Wang, Zhugang Wang, Li Zhou
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Low power and high-speed quadrate node upset tolerant latch design using CNTFET [PDF]
Scientific ReportsScalability, leakage, short-channel effects, and reliability problems are some of the difficulties facing the semiconductor industry as it continues to experience a reduction in size.
Shaik Asiya, Satheesh Kumar S
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