Results 21 to 30 of about 16,144 (237)

A low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology

IET Circuits, Devices and Systems, 2021
Conventional flip‐flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation‐hardened flip‐flops (FFs) based on techniques like triple modular redundancy, dual interlocked ...
Sabavat Satheesh Kumar, Kumaravel Sundaram, Sanjeevikumar Padmanaban, Jens Bo Holm‐Nielsen, Frede Blaabjerg   +4 more
doaj   +1 more source

Upper Stage Rocket Computer Technology Based on Multi-redundancy and Reconfigurable [PDF]

Jisuanji gongcheng, 2016
Aiming at features of the upper stage rocket computer,such as strong real-time property,high reliability and space radiation resistance,a new computer technology based on redundanly and reconfiguration is proposed.This paper describes the key ...
QU Xi,HUANG Huimin,ZHANG Ning,YU Guoqiang
doaj   +1 more source

Determination of the Sensitive Volume and Critical Charge for Induction of SEU in Nanometer SRAMs [PDF]

فصلنامه علوم و فناوری فضایی, 2023
In this paper, the sensitive volume and critical charge of a 65-nm CMOS SRAM as two important quantities in Single Event Upset (SEU) calculations have been determined. SEU is the most common event in space investigations.
Gholamreza Raisali, Masume Soleimaninia, Amir Moslehi   +2 more
doaj   +1 more source

Monitor of the single event upsets and linear energy transfer of space radiation on the Beidou navigation satellites

Open Astronomy, 2023
The single event effect caused by space heavy ion radiation is one of the important factors affecting the safety and operation of spacecraft on orbit.
Zhang Binquan, Zhang Shenyi, Shen Guohong, Tuo Changsheng, Zhang Xin, Zhang Huanxin, Quan Lin, Tian Chao, Hou Donghui, Zhou Ping, Ji Wentao   +10 more
doaj   +1 more source

Single-Event Upset Cross-Section Trends for D-FFs at the 5- and 7-nm Bulk FinFET Technology Nodes

IEEE Transactions on Nuclear Science, 2023
At each advanced technology node, it is crucial to characterize and understand the mechanisms affecting performance and reliability. Scaling for all nodes prior to the 5-nm bulk FinFET node had resulted in a decrease in single-event upset (SEU) cross ...
Y. Xiong, N. Pieper, A. Feeley, B. Narasimham, D. Ball, B. Bhuva   +5 more
semanticscholar   +1 more source

Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications

IEEE Access, 2023
Deep sub-micron memory devices play a crucial role in space electronic applications due to their susceptibility to single-event upset and double-node upset types of soft errors. When a charged particle from space hit a scaled memory circuit, the critical
Pavan Kumar Mukku, Rohit Lorenzo
doaj   +1 more source

Solar Particle Event and Single Event Upset Prediction from SRAM-Based Monitor and Supervised Machine Learning

IEEE Transactions on Emerging Topics in Computing, 2022
The intensity of cosmic radiation may differ over five orders of magnitude within a few hours or days during the Solar Particle Events (SPEs), thus increasing for several orders of magnitude the probability of Single Event Upsets (SEUs) in space-borne ...
Junchao Chen, T. Lange, M. Andjelković, A. Simevski, Li Lu, M. Krstic   +5 more
semanticscholar   +1 more source

Radiation Hardened NULL Convention Logic Asynchronous Circuit Design

Journal of Low Power Electronics and Applications, 2015
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss.
Liang Zhou, Scott C. Smith, Jia Di
doaj   +1 more source

Dynamic Partial Reconfiguration Project for the Anti-single Event Effect Based on the Soft Error Mitigation

Nantong Daxue xuebao. Ziran kexue ban, 2020
With the wide application of FPGA(field programmable gate array) based on the SRAM(static randomaccess memory) in the aerospace field, the probability of SEU(single event upset) increases gradually while the FPGAs are exposed in irradiation environment ...
XIE Da;DONG Yiping;WANG Lan;CAO Jinde;GUO Junjie
doaj   +1 more source

Single-Event Upset Analysis and Protection in High Speed Circuits [PDF]

, 2006
The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at
Benso, Alfredo, Di Carlo, Stefano, Di Natale, Giorgio, Hosseinabady, M., Lofti-Kamran, P., Prinetto, Paolo Ernesto   +5 more
core   +1 more source