Results 161 to 170 of about 10,650 (234)
Comparative Analysis of LiDAR-SLAM Systems: A Study of a Motorized Optomechanical LiDAR and an MEMS Scanner LiDAR. [PDF]
Sensors (Basel)Fortuna S +3 more
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Fast Coincidence Filter for Silicon Photomultiplier Dark Count Rate Rejection. [PDF]
Sensors (Basel)Real D +7 more
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10-km passive drone detection using broadband quantum compressed sensing imaging. [PDF]
Light Sci ApplWu S +16 more
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Design and implementation of a high resolution, multi-hit time-to-digital converter (TDC) on FPGA
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2011 IEEE International Instrumentation and Measurement Technology Conference, 2011
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
S. Al-Ahdab +2 more
semanticscholar +4 more sources
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
S. Al-Ahdab +2 more
semanticscholar +4 more sources
Quantization noise improvement of Time to Digital converter (TDC) for ADPLL
2009 IEEE International Symposium on Circuits and Systems, 2009A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒ c , based on a input reference frequency ...
J. Tangudu +8 more
semanticscholar +2 more sources
NORCHIP 2010, 2010
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
S. Al-Ahdab +2 more
semanticscholar +2 more sources
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
S. Al-Ahdab +2 more
semanticscholar +2 more sources
Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS
2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver.
Popong Effendrik +4 more
semanticscholar +2 more sources
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
semanticscholar +2 more sources
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
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A synthesizable Time to Digital Converter (TDC) with MIMO spatial oversampling method
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015A 7 ps/LSB, 0.02 mm2 and 3.9 mW@50MHz Time to Digital Converter architecture with novel MIMO spatial oversampling method is proposed as part of an effort to implement an all-digital PLL (ADPLL) by replacing the phase frequency detector in phase locked loops (PLL).
Yalcin Balcioglu, Günhan Dündar
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